- fix incorrect parsing of whitespace in command.c (thanks to Magnus Lundin)

- fix infinite recursion in target_init_handler (thanks to jw and Magnus Lundin)
- fix CFI flash handlign with buswidth < 32bit (thanks to Daniele Orio for reporting this)
- add support for reading JTAG device id (currently only as debug output on startup)
- cleaned up handling of EmbeddedICE registers. Supported functionality and register size now determined by EmbeddedICE version number.
- small cleanups/fixes


git-svn-id: svn://svn.berlios.de/openocd/trunk@124 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/arm7_9_common.c

@@ -2388,7 +2388,11 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	arm7_9->wp1_used = 0;
 	arm7_9->force_hw_bkpts = 0;
 	arm7_9->use_dbgrq = 0;
+	
 	arm7_9->has_etm = 0;
+	arm7_9->has_single_step = 0;
+	arm7_9->has_monitor_mode = 0;
+	arm7_9->has_vector_catch = 0;
 	
 	arm7_9->reinit_embeddedice = 0;
 	

src/target/arm7_9_common.h

@@ -45,7 +45,11 @@ typedef struct arm7_9_common_s
 	int force_hw_bkpts;
 	int dbgreq_adjust_pc;
 	int use_dbgrq;
+	
 	int has_etm;
+	int has_single_step;
+	int has_monitor_mode;
+	int has_vector_catch;
 	
 	int reinit_embeddedice;
 	

src/target/arm7tdmi.c

@@ -742,7 +742,7 @@ void arm7tdmi_build_reg_cache(target_t *target)
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 	armv4_5->core_cache = (*cache_p);
 	
-	(*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 0);
+	(*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 	arm7_9->eice_cache = (*cache_p)->next;
 	
 	if (arm7_9->has_etm)
@@ -750,14 +750,6 @@ void arm7tdmi_build_reg_cache(target_t *target)
 		(*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
 		arm7_9->etm_cache = (*cache_p)->next->next;
 	}
-		
-	if (arch_info->has_monitor_mode)
-		(*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
-	else
-		(*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 3;
-	
-	(*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
-
 }
 
 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
@@ -828,30 +820,20 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c
 	arm7_9->sw_bkpts_enabled = 0;
 	arm7_9->dbgreq_adjust_pc = 2;
 	arm7_9->arch_info = arm7tdmi;
-	
-	arm7tdmi->has_monitor_mode = 0;
+
 	arm7tdmi->arch_info = NULL;
 	arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 	
 	if (variant)
 	{
-		if (strcmp(variant, "arm7tdmi-s_r4") == 0)
-			arm7tdmi->has_monitor_mode = 1;
-		else if (strcmp(variant, "arm7tdmi_r4") == 0)
-			arm7tdmi->has_monitor_mode = 1;
-		else if (strcmp(variant, "lpc2000") == 0)
-		{
-			arm7tdmi->has_monitor_mode = 1;
-			has_etm = 1;
-		}
 		arm7tdmi->variant = strdup(variant);
 	}
 	else
+	{
 		arm7tdmi->variant = strdup("");
+	}
 	
 	arm7_9_init_arch_info(target, arm7_9);
-	
-	arm7_9->has_etm = has_etm;
 
 	return ERROR_OK;
 }

src/target/arm7tdmi.h

@@ -33,7 +33,6 @@ typedef struct arm7tdmi_common_s
 {
 	int common_magic;
 	char *variant;
-	int has_monitor_mode;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm7tdmi_common_t;

src/target/arm920t.c

@@ -701,7 +701,7 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chai
 	arm920t->preserve_cache = 0;
 	
 	/* override hw single-step capability from ARM9TDMI */
-	arm9tdmi->has_single_step = 1;
+	arm7_9->has_single_step = 1;
 	
 	return ERROR_OK;
 }

src/target/arm966e.c

@@ -91,9 +91,6 @@ int arm966e_assert_reset(target_t *target)
 	arm966e_common_t *arm966e = arm9tdmi->arch_info;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int retval;
-	int trst_asserted_with_srt = 0;
-	
-	arm966e->monitor_mode_set = 1;
 	
 	DEBUG("target->state: %s", target_state_strings[target->state]);
 	
@@ -121,7 +118,6 @@ int arm966e_assert_reset(target_t *target)
 			{
 				WARNING("srst resets test logic, too");
 				retval = jtag_add_reset(1, 1);
-				trst_asserted_with_srt = 1;
 			}
 		}
 	}
@@ -133,7 +129,6 @@ int arm966e_assert_reset(target_t *target)
 			{
 				WARNING("srst resets test logic, too");
 				retval = jtag_add_reset(1, 1);
-				trst_asserted_with_srt = 1;
 			}
 			
 			if (retval == ERROR_JTAG_RESET_CANT_SRST)
@@ -153,23 +148,6 @@ int arm966e_assert_reset(target_t *target)
 	jtag_add_sleep(50000);
 	
 	armv4_5_invalidate_core_regs(target);
-
-	if( trst_asserted_with_srt == 0 )
-	{
-		DEBUG("monitor mode needs clearing");
-		
-		/* arm9e monitor mode enabled at reset */
-		embeddedice_read_reg(dbg_ctrl);
-		jtag_execute_queue();
-		
-		if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1))
-		{
-			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0);
-			embeddedice_store_reg(dbg_ctrl);
-			DEBUG("monitor mode disabled");
-		}
-		arm966e->monitor_mode_set = 0;
-	}
 	
 	return ERROR_OK;
 }
@@ -184,23 +162,6 @@ int arm966e_deassert_reset(target_t *target)
 	
 	arm7_9_deassert_reset( target );
 	
-	if( arm966e->monitor_mode_set == 1 )
-	{
-		DEBUG("monitor mode needs clearing");
-		
-		/* arm9e monitor mode enabled at reset */
-		embeddedice_read_reg(dbg_ctrl);
-		jtag_execute_queue();
-				
-		if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1))
-		{
-			buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0);
-			embeddedice_store_reg(dbg_ctrl);
-			arm966e->monitor_mode_set = 0;
-			DEBUG("monitor mode disabled");
-		}
-	}
-	
 	return ERROR_OK;
 }
 
@@ -226,9 +187,6 @@ int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chai
 	arm9tdmi->arch_info = arm966e;
 	arm966e->common_magic = ARM966E_COMMON_MAGIC;
 	
-	arm9tdmi->has_single_step = 0;
-	arm9tdmi->has_monitor_mode = 1;
-	
 	return ERROR_OK;
 }
 

src/target/arm966e.h

@@ -33,7 +33,6 @@ typedef struct arm966e_common_s
 	int common_magic;
 	arm9tdmi_common_t arm9tdmi_common;
 	u32 cp15_control_reg;
-	int monitor_mode_set;
 } arm966e_common_t;
 
 #endif /* ARM966E_H */

src/target/arm9tdmi.c

@@ -788,7 +788,7 @@ void arm9tdmi_enable_single_step(target_t *target)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 	
-	if (arm9->has_single_step)
+	if (arm7_9->has_single_step)
 	{
 		buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 		embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
@@ -806,7 +806,7 @@ void arm9tdmi_disable_single_step(target_t *target)
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 	
-	if (arm9->has_single_step)
+	if (arm7_9->has_single_step)
 	{
 		buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 		embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
@@ -832,16 +832,10 @@ void arm9tdmi_build_reg_cache(target_t *target)
 	armv4_5->core_cache = (*cache_p);
 	
 	/* one extra register (vector catch) */
-	(*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 1);
+	(*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 	arm7_9->eice_cache = (*cache_p)->next;
-	
-	if (arm9tdmi->has_monitor_mode)
-		(*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
-	else
-		(*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 4;
-	
-	(*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
 
+#if 0	
 	(*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
 	(*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
 	(*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
@@ -851,7 +845,7 @@ void arm9tdmi_build_reg_cache(target_t *target)
 	(*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
 	vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
 	vec_catch_arch_info->addr = 0x2;
-	
+#endif
 }
 
 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
@@ -923,27 +917,24 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int c
 	arm7_9->arch_info = arm9tdmi;
 	
 	arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
-	arm9tdmi->has_monitor_mode = 0;
-	arm9tdmi->has_single_step = 0;
 	arm9tdmi->arch_info = NULL;
 
 	if (variant)
 	{
-		if (strcmp(variant, "arm920t") == 0)
-			arm9tdmi->has_single_step = 1;
-		else if (strcmp(variant, "arm922t") == 0)
-			arm9tdmi->has_single_step = 1;
-		else if (strcmp(variant, "arm940t") == 0)
-			arm9tdmi->has_single_step = 1;
 		arm9tdmi->variant = strdup(variant);
 	}
 	else
+	{
 		arm9tdmi->variant = strdup("");
+	}
 	
 	arm7_9_init_arch_info(target, arm7_9);
 
 	/* override use of DBGRQ, this is safe on ARM9TDMI */
 	arm7_9->use_dbgrq = 1;
+
+	/* all ARM9s have the vector catch register */
+	arm7_9->has_vector_catch = 1;
 	
 	return ERROR_OK;
 }

src/target/arm9tdmi.h

@@ -33,8 +33,6 @@ typedef struct arm9tdmi_common_s
 {
 	int common_magic;
 	char *variant;
-	int has_monitor_mode;
-	int has_single_step;
 	void *arch_info;
 	arm7_9_common_t arm7_9_common;
 } arm9tdmi_common_t;

src/target/embeddedice.c

@@ -48,7 +48,8 @@ int embeddedice_reg_arch_info[] =
 {
 	0x0, 0x1, 0x4, 0x5,
 	0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+	0x2
 };
 
 char* embeddedice_reg_list[] =
@@ -71,7 +72,9 @@ char* embeddedice_reg_list[] =
 	"watch 1 data value",
 	"watch 1 data mask",
 	"watch 1 control value",
-	"watch 1 control mask"
+	"watch 1 control mask",
+	
+	"vector catch"
 };
 
 int embeddedice_reg_arch_type = -1;
@@ -83,18 +86,25 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
 int embeddedice_write_reg(reg_t *reg, u32 value);
 int embeddedice_read_reg(reg_t *reg);
 
-reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg)
+reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
 {
 	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = NULL;
 	embeddedice_reg_t *arch_info = NULL;
-	int num_regs = 16 + extra_reg;
+	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	int num_regs;
 	int i;
+	int eice_version = 0;
 	
 	/* register a register arch-type for EmbeddedICE registers only once */
 	if (embeddedice_reg_arch_type == -1)
 		embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
 	
+	if (arm7_9->has_vector_catch)
+		num_regs = 17;
+	else
+		num_regs = 16;
+		
 	/* the actual registers are kept in two arrays */
 	reg_list = calloc(num_regs, sizeof(reg_t));
 	arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
@@ -106,7 +116,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info
 	reg_cache->num_regs = num_regs;
 	
 	/* set up registers */
-	for (i = 0; i < num_regs - extra_reg; i++)
+	for (i = 0; i < num_regs; i++)
 	{
 		reg_list[i].name = embeddedice_reg_list[i];
 		reg_list[i].size = 32;
@@ -121,12 +131,49 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info
 		arch_info[i].jtag_info = jtag_info;
 	}
 	
-	/* there may be one extra reg (Abort status (ARM7 rev4) or Vector catch (ARM9)) */
-	if (extra_reg)
+	/* identify EmbeddedICE version by reading DCC control register */
+	embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
+	jtag_execute_queue();
+	
+	eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
+	
+	switch (eice_version)
 	{
-		reg_list[num_regs - 1].arch_info = &arch_info[num_regs - 1];
-		reg_list[num_regs - 1].arch_type = embeddedice_reg_arch_type;
-		arch_info[num_regs - 1].jtag_info = jtag_info;
+		case 1:
+			reg_list[EICE_DBG_CTRL].size = 3;
+			reg_list[EICE_DBG_STAT].size = 5;
+			break;
+		case 2:
+			reg_list[EICE_DBG_CTRL].size = 4;
+			reg_list[EICE_DBG_STAT].size = 5;
+			arm7_9->has_single_step = 1;
+			break;
+		case 3:
+			ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); 
+			reg_list[EICE_DBG_CTRL].size = 6;
+			reg_list[EICE_DBG_STAT].size = 5;
+			arm7_9->has_single_step = 1;
+			arm7_9->has_monitor_mode = 1;
+			break;
+		case 4:
+			reg_list[EICE_DBG_CTRL].size = 6;
+			reg_list[EICE_DBG_STAT].size = 5;
+			arm7_9->has_monitor_mode = 1;
+			break;
+		case 5:
+			reg_list[EICE_DBG_CTRL].size = 6;
+			reg_list[EICE_DBG_STAT].size = 5;
+			arm7_9->has_single_step = 1;
+			arm7_9->has_monitor_mode = 1;
+			break;
+		case 6:
+			reg_list[EICE_DBG_CTRL].size = 6;
+			reg_list[EICE_DBG_STAT].size = 10;
+			arm7_9->has_single_step = 1;
+			arm7_9->has_monitor_mode = 1;
+			break;
+		default:
+			ERROR("unknown EmbeddedICE version (comms ctrl: 0x%4.4x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 	
 	return reg_cache;

src/target/embeddedice.h

@@ -23,6 +23,7 @@
 #include "target.h"
 #include "register.h"
 #include "arm_jtag.h"
+#include "arm7_9_common.h"
 
 enum
 {
@@ -42,7 +43,6 @@ enum
 	EICE_W1_DATA_MASK = 13,
 	EICE_W1_CONTROL_VALUE = 14,
 	EICE_W1_CONTROL_MASK = 15,
-	EICE_ABT_STATUS = 16,
 	EICE_VEC_CATCH = 16
 };
 
@@ -57,6 +57,7 @@ enum
 
 enum
 {
+	EICE_DBG_STATUS_IJBIT = 5,
 	EICE_DBG_STATUS_ITBIT = 4,
 	EICE_DBG_STATUS_SYSCOMP = 3,
 	EICE_DBG_STATUS_IFEN = 2,
@@ -89,7 +90,7 @@ typedef struct embeddedice_reg_s
 	arm_jtag_t *jtag_info;
 } embeddedice_reg_t;
 
-extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);
+extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9);
 extern int embeddedice_read_reg(reg_t *reg);
 extern int embeddedice_write_reg(reg_t *reg, u32 value);
 extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);

src/target/target.c

@@ -209,6 +209,8 @@ int target_init_handler(struct target_s *target, enum target_event event, void *
 	
 	if ((event == TARGET_EVENT_HALTED) && (target->reset_script))
 	{
+		target_unregister_event_callback(target_init_handler, priv);
+
 		script = fopen(target->reset_script, "r");
 		if (!script)
 		{
@@ -221,8 +223,6 @@ int target_init_handler(struct target_s *target, enum target_event event, void *
 		fclose(script);
 
 		jtag_execute_queue();
-
-		target_unregister_event_callback(target_init_handler, priv);
 	}
 	
 	return ERROR_OK;