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target: riscv: move the SMP commands under riscv

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For all the targets that support SMP, the sub-commands 'smp' and
'smp_gdb' are under the arch name:
- aarch64 smp
- cortex_a smp
- cortex_m smp
- esp32 smp
- mips_m4k smp

Keep consistency among OpenOCD commands, and move under the arch
name 'riscv' the SMP subcommands.

Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9165
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2025-10-07 14:03:15 +02:00
committed by Tomas Vanek
parent 8c41070415
commit 52ac91a73e
2 changed files with 6 additions and 6 deletions
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6
doc/openocd.texi
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@@ -11800,16 +11800,16 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
and DBUS registers, respectively.
@end deffn
@deffn {Command} {smp} [on|off]
@deffn {Command} {riscv smp} [on|off]
Display, enable or disable SMP handling mode. This command is needed only if
user wants to temporary @b{disable} SMP handling for an existing SMP group
(see @code{aarch64 smp} for additional information). To define an SMP
group the command @code{target smp} should be used.
@end deffn
@deffn {Command} {smp_gdb} [core_id]
@deffn {Command} {riscv smp_gdb} [core_id]
Display/set the current core displayed in GDB. This is needed only if
@code{smp} was used.
@code{riscv smp} was used.
@end deffn
@deffn {Config Command} {riscv use_bscan_tunnel} width [type]