- merged mips target into svn trunk
git-svn-id: svn://svn.berlios.de/openocd/trunk@874 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
642
src/target/mips_m4k.c
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642
src/target/mips_m4k.c
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@@ -0,0 +1,642 @@
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/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "mips32.h"
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#include "mips_m4k.h"
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#include "jtag.h"
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#include "log.h"
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#include <stdlib.h>
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#include <string.h>
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/* cli handling */
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/* forward declarations */
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int mips_m4k_poll(target_t *target);
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int mips_m4k_halt(struct target_s *target);
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int mips_m4k_soft_reset_halt(struct target_s *target);
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int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
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int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
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int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
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int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int mips_m4k_quit();
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int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
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int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target);
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int mips_m4k_assert_reset(target_t *target);
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int mips_m4k_deassert_reset(target_t *target);
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target_type_t mips_m4k_target =
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{
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.name = "mips_m4k",
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.poll = mips_m4k_poll,
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.arch_state = mips32_arch_state,
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.target_request_data = NULL,
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.halt = mips_m4k_halt,
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.resume = mips_m4k_resume,
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.step = mips_m4k_step,
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.assert_reset = mips_m4k_assert_reset,
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.deassert_reset = mips_m4k_deassert_reset,
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.soft_reset_halt = mips_m4k_soft_reset_halt,
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.get_gdb_reg_list = mips32_get_gdb_reg_list,
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.read_memory = mips_m4k_read_memory,
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.write_memory = mips_m4k_write_memory,
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.bulk_write_memory = mips_m4k_bulk_write_memory,
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.checksum_memory = NULL,
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.blank_check_memory = NULL,
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.run_algorithm = mips32_run_algorithm,
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.add_breakpoint = mips_m4k_add_breakpoint,
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.remove_breakpoint = mips_m4k_remove_breakpoint,
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.add_watchpoint = mips_m4k_add_watchpoint,
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.remove_watchpoint = mips_m4k_remove_watchpoint,
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.register_commands = mips_m4k_register_commands,
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.target_command = mips_m4k_target_command,
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.init_target = mips_m4k_init_target,
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.examine = mips_m4k_examine,
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.quit = mips_m4k_quit
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};
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int mips_m4k_debug_entry(target_t *target)
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{
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u32 debug_reg;
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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/* read debug register */
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mips_ejtag_read_debug(ejtag_info, &debug_reg);
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP))
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{
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// if (cortex_m3->nvic_dfsr & DFSR_BKPT)
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// {
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// target->debug_reason = DBG_REASON_BREAKPOINT;
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// if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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// target->debug_reason = DBG_REASON_WPTANDBKPT;
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// }
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// else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
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// target->debug_reason = DBG_REASON_WATCHPOINT;
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}
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if (debug_reg & EJTAG_DEBUG_DSS)
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{
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/* stopped due to single step - clear step bit */
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mips_ejtag_config_step(ejtag_info, 0);
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}
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mips32_save_context(target);
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LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", \
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*(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), target_state_strings[target->state]);
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return ERROR_OK;
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}
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int mips_m4k_poll(target_t *target)
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{
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int retval;
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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/* read ejtag control reg */
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jtag_add_end_state(TAP_RTI);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
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if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
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{
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if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
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{
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jtag_add_end_state(TAP_RTI);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
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target->state = TARGET_HALTED;
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if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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else if (target->state == TARGET_DEBUG_RUNNING)
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{
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target->state = TARGET_HALTED;
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if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
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}
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}
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else
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{
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target->state = TARGET_RUNNING;
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}
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if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
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{
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/* we have detected a reset, clear flag
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* otherwise ejtag will not work */
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jtag_add_end_state(TAP_RTI);
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ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
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mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
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LOG_DEBUG("Reset Detected");
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}
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// LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
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return ERROR_OK;
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}
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int mips_m4k_halt(struct target_s *target)
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{
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
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if (target->state == TARGET_HALTED)
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{
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LOG_DEBUG("target was already halted");
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return ERROR_OK;
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}
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if (target->state == TARGET_UNKNOWN)
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{
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LOG_WARNING("target was in unknown state when halt was requested");
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}
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if (target->state == TARGET_RESET)
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{
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if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
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{
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LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
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return ERROR_TARGET_FAILURE;
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}
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else
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{
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/* we came here in a reset_halt or reset_init sequence
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* debug entry was already prepared in mips32_prepare_reset_halt()
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*/
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target->debug_reason = DBG_REASON_DBGRQ;
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return ERROR_OK;
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}
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}
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/* break processor */
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mips_ejtag_enter_debug(ejtag_info);
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target->debug_reason = DBG_REASON_DBGRQ;
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return ERROR_OK;
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}
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int mips_m4k_assert_reset(target_t *target)
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{
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
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if (!(jtag_reset_config & RESET_HAS_SRST))
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{
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LOG_ERROR("Can't assert SRST");
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return ERROR_FAIL;
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}
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if (target->reset_halt)
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{
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/* use hardware to catch reset */
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jtag_add_end_state(TAP_RTI);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
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}
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else
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{
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jtag_add_end_state(TAP_RTI);
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
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}
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/* here we should issue a srst only, but we may have to assert trst as well */
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if (jtag_reset_config & RESET_SRST_PULLS_TRST)
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{
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jtag_add_reset(1, 1);
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}
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else
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{
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jtag_add_reset(0, 1);
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}
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target->state = TARGET_RESET;
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jtag_add_sleep(50000);
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mips32_invalidate_core_regs(target);
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return ERROR_OK;
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}
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int mips_m4k_deassert_reset(target_t *target)
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{
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LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
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/* deassert reset lines */
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jtag_add_reset(0, 0);
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return ERROR_OK;
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}
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int mips_m4k_soft_reset_halt(struct target_s *target)
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{
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/* TODO */
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return ERROR_OK;
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}
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int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
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{
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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breakpoint_t *breakpoint = NULL;
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u32 resume_pc;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (!debug_execution)
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{
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target_free_all_working_areas(target);
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mips_m4k_enable_breakpoints(target);
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mips_m4k_enable_watchpoints(target);
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}
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/* current = 1: continue on current pc, otherwise continue at <address> */
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if (!current)
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{
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buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
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mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
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mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
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}
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resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
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mips32_restore_context(target);
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/* the front-end may request us not to handle breakpoints */
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if (handle_breakpoints)
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{
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/* Single step past breakpoint at current address */
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if ((breakpoint = breakpoint_find(target, resume_pc)))
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{
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LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
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mips_m4k_unset_breakpoint(target, breakpoint);
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//mips_m4k_single_step_core(target);
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mips_m4k_set_breakpoint(target, breakpoint);
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}
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}
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/* exit debug mode - enable interrupts if required */
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mips_ejtag_exit_debug(ejtag_info, !debug_execution);
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/* registers are now invalid */
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mips32_invalidate_core_regs(target);
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if (!debug_execution)
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{
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target->state = TARGET_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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LOG_DEBUG("target resumed at 0x%x", resume_pc);
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}
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else
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{
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target->state = TARGET_DEBUG_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
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LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
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}
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return ERROR_OK;
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}
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int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
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{
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/* get pointers to arch-specific information */
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mips32_common_t *mips32 = target->arch_info;
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mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
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breakpoint_t *breakpoint = NULL;
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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||||
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/* current = 1: continue on current pc, otherwise continue at <address> */
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if (!current)
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buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
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||||
/* the front-end may request us not to handle breakpoints */
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||||
if (handle_breakpoints)
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||||
if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
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mips_m4k_unset_breakpoint(target, breakpoint);
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||||
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||||
/* restore context */
|
||||
mips32_restore_context(target);
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||||
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||||
/* configure single step mode */
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||||
mips_ejtag_config_step(ejtag_info, 1);
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||||
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||||
target->debug_reason = DBG_REASON_SINGLESTEP;
|
||||
|
||||
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
|
||||
|
||||
/* exit debug mode */
|
||||
mips_ejtag_exit_debug(ejtag_info, 1);
|
||||
|
||||
/* registers are now invalid */
|
||||
mips32_invalidate_core_regs(target);
|
||||
|
||||
if (breakpoint)
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||||
mips_m4k_set_breakpoint(target, breakpoint);
|
||||
|
||||
LOG_DEBUG("target stepped ");
|
||||
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||||
mips_m4k_debug_entry(target);
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||||
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
void mips_m4k_enable_breakpoints(struct target_s *target)
|
||||
{
|
||||
breakpoint_t *breakpoint = target->breakpoints;
|
||||
|
||||
/* set any pending breakpoints */
|
||||
while (breakpoint)
|
||||
{
|
||||
if (breakpoint->set == 0)
|
||||
mips_m4k_set_breakpoint(target, breakpoint);
|
||||
breakpoint = breakpoint->next;
|
||||
}
|
||||
}
|
||||
|
||||
int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
|
||||
{
|
||||
/* TODO */
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
void mips_m4k_enable_watchpoints(struct target_s *target)
|
||||
{
|
||||
watchpoint_t *watchpoint = target->watchpoints;
|
||||
|
||||
/* set any pending watchpoints */
|
||||
while (watchpoint)
|
||||
{
|
||||
if (watchpoint->set == 0)
|
||||
mips_m4k_set_watchpoint(target, watchpoint);
|
||||
watchpoint = watchpoint->next;
|
||||
}
|
||||
}
|
||||
|
||||
int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
|
||||
{
|
||||
mips32_common_t *mips32 = target->arch_info;
|
||||
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
|
||||
|
||||
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_WARNING("target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
/* sanitize arguments */
|
||||
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
|
||||
return ERROR_INVALID_ARGUMENTS;
|
||||
|
||||
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
|
||||
return ERROR_TARGET_UNALIGNED_ACCESS;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 4:
|
||||
case 2:
|
||||
case 1:
|
||||
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
exit(-1);
|
||||
break;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
|
||||
{
|
||||
mips32_common_t *mips32 = target->arch_info;
|
||||
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
|
||||
|
||||
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
LOG_WARNING("target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
/* sanitize arguments */
|
||||
if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
|
||||
return ERROR_INVALID_ARGUMENTS;
|
||||
|
||||
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
|
||||
return ERROR_TARGET_UNALIGNED_ACCESS;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 4:
|
||||
case 2:
|
||||
case 1:
|
||||
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
exit(-1);
|
||||
break;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = mips32_register_commands(cmd_ctx);
|
||||
return retval;
|
||||
}
|
||||
|
||||
int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
|
||||
{
|
||||
mips32_build_reg_cache(target);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_quit()
|
||||
{
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, char *variant)
|
||||
{
|
||||
mips32_common_t *mips32 = &mips_m4k->mips32_common;
|
||||
|
||||
if (variant)
|
||||
{
|
||||
mips_m4k->variant = strdup(variant);
|
||||
}
|
||||
else
|
||||
{
|
||||
mips_m4k->variant = strdup("");
|
||||
}
|
||||
|
||||
mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
|
||||
|
||||
/* initialize mips4k specific info */
|
||||
mips32_init_arch_info(target, mips32, chain_pos, variant);
|
||||
mips32->arch_info = mips_m4k;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
|
||||
{
|
||||
int chain_pos;
|
||||
char *variant = NULL;
|
||||
mips_m4k_common_t *mips_m4k = malloc(sizeof(mips_m4k_common_t));
|
||||
|
||||
if (argc < 4)
|
||||
{
|
||||
LOG_ERROR("'target mips4k' requires at least one additional argument");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
chain_pos = strtoul(args[3], NULL, 0);
|
||||
|
||||
if (argc >= 5)
|
||||
variant = args[4];
|
||||
|
||||
mips_m4k_init_arch_info(target, mips_m4k, chain_pos, variant);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target)
|
||||
{
|
||||
int retval;
|
||||
mips32_common_t *mips32 = target->arch_info;
|
||||
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
|
||||
u32 idcode = 0;
|
||||
|
||||
target->type->examined = 1;
|
||||
|
||||
mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
|
||||
|
||||
if (((idcode >> 1) & 0x7FF) == 0x29)
|
||||
{
|
||||
/* we are using a pic32mx so select ejtag port
|
||||
* as it is not selected by default */
|
||||
mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
|
||||
LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
|
||||
}
|
||||
|
||||
/* init rest of ejtag interface */
|
||||
if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
|
||||
{
|
||||
return mips_m4k_write_memory(target, address, 4, count, buffer);
|
||||
}
|
||||
Reference in New Issue
Block a user