auracaster/openocd
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John McCarthy <jgmcc@magma.ca> cleans up the usage of the

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ejtag_info->ejtag_ctrl variable.  It was being overwritten by the value read back from the EJTAG CONTROL register.  Because of the way this register works you do not want to use the value returned to write the register, you always want to write the bits explicitly.

The second patch just reduces the DMA retries to 0 in anticipation of removing the retry code altogether.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1049 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
2008-10-14 06:21:17 +00:00
parent 3600e7c6e0
commit 539527ab74
5 changed files with 81 additions and 77 deletions
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13
src/target/mips_m4k.c
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@@ -132,13 +132,14 @@ int mips_m4k_poll(target_t *target)
int retval;
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
/* read ejtag control reg */
jtag_add_end_state(TAP_RTI);
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST)
if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
@@ -167,19 +168,19 @@ int mips_m4k_poll(target_t *target)
target->state = TARGET_RUNNING;
}
if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC)
if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI);
ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC;
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
// LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl);
// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
return ERROR_OK;
}