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target: riscv: Drop new typedefs added by the updated riscv-debug-spec files

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The advantage of this patch is that it brings the new code closer to
OpenOCD coding style - the disadvantage is that it involves modifying
autogenerated files, making it harder to drop in new versions when
riscv-debug-spec changes.

Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8896
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This commit is contained in:
Bernhard Rosenkränzer
2025-05-06 01:34:18 +02:00
committed by Tomas Vanek
parent 5754aebc49
commit 56141bb349
6 changed files with 496 additions and 496 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/riscv/batch.c
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@@ -172,7 +172,7 @@ static unsigned int decode_dmi(const struct riscv_batch *batch, char *text,
for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) { for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) {
if (riscv_get_dmi_address(batch->target, description[i].address) if (riscv_get_dmi_address(batch->target, description[i].address)
== address) { == address) {
const riscv_debug_reg_ctx_t context = { const struct riscv_debug_reg_ctx context = {
.XLEN = { .value = 0, .is_set = false }, .XLEN = { .value = 0, .is_set = false },
.DXLEN = { .value = 0, .is_set = false }, .DXLEN = { .value = 0, .is_set = false },
.abits = { .value = 0, .is_set = false }, .abits = { .value = 0, .is_set = false },

940
src/target/riscv/debug_defines.c
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File diff suppressed because it is too large Load Diff

24
src/target/riscv/debug_defines.h
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@@ -3204,7 +3204,7 @@ enum riscv_debug_reg_ordinal {
AC_ACCESS_MEMORY_ORDINAL, AC_ACCESS_MEMORY_ORDINAL,
VIRT_PRIV_ORDINAL VIRT_PRIV_ORDINAL
}; };
typedef struct { struct riscv_debug_reg_ctx {
struct { struct {
unsigned int value; int is_set; unsigned int value; int is_set;
} DXLEN; } DXLEN;
@@ -3214,21 +3214,21 @@ typedef struct {
struct { struct {
unsigned int value; int is_set; unsigned int value; int is_set;
} abits; } abits;
} riscv_debug_reg_ctx_t; };
typedef struct { struct riscv_debug_reg_field_info {
const char *name; const char *name;
unsigned int lsb; // inclusive unsigned int lsb; // inclusive
unsigned int msb; // inclusive unsigned int msb; // inclusive
const char **values; // If non-NULL, array of human-readable string for each possible value const char **values; // If non-NULL, array of human-readable string for each possible value
} riscv_debug_reg_field_info_t; };
typedef struct riscv_debug_reg_field_list_t { struct riscv_debug_reg_field_list {
riscv_debug_reg_field_info_t field; struct riscv_debug_reg_field_info field;
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t context); struct riscv_debug_reg_field_list (*get_next)(struct riscv_debug_reg_ctx context);
} riscv_debug_reg_field_list_t; };
typedef struct { struct riscv_debug_reg_info {
const char *name; const char *name;
struct riscv_debug_reg_field_list_t (* const get_fields_head)(riscv_debug_reg_ctx_t context); struct riscv_debug_reg_field_list (* const get_fields_head)(struct riscv_debug_reg_ctx context);
} riscv_debug_reg_info_t; };
riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal); struct riscv_debug_reg_info get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal);
#endif #endif

14
src/target/riscv/debug_reg_printer.c
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@@ -43,7 +43,7 @@ static unsigned int riscv_debug_reg_field_value_to_s(char *buf, unsigned int off
} }
static unsigned int riscv_debug_reg_field_to_s(char *buf, unsigned int offset, static unsigned int riscv_debug_reg_field_to_s(char *buf, unsigned int offset,
riscv_debug_reg_field_info_t field, riscv_debug_reg_ctx_t context, struct riscv_debug_reg_field_info field, struct riscv_debug_reg_ctx context,
uint64_t field_value) uint64_t field_value)
{ {
const unsigned int name_len = get_len_or_sprintf(buf, offset, "%s=", field.name); const unsigned int name_len = get_len_or_sprintf(buf, offset, "%s=", field.name);
@@ -52,7 +52,7 @@ static unsigned int riscv_debug_reg_field_to_s(char *buf, unsigned int offset,
field.values, field_value); field.values, field_value);
} }
static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field, uint64_t value) static uint64_t riscv_debug_reg_field_value(struct riscv_debug_reg_field_info field, uint64_t value)
{ {
assert(field.msb < 64); assert(field.msb < 64);
assert(field.msb >= field.lsb); assert(field.msb >= field.lsb);
@@ -61,14 +61,14 @@ static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field,
} }
static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset, static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex), struct riscv_debug_reg_field_list (*get_next)(struct riscv_debug_reg_ctx contex),
riscv_debug_reg_ctx_t context, uint64_t value, struct riscv_debug_reg_ctx context, uint64_t value,
enum riscv_debug_reg_show show) enum riscv_debug_reg_show show)
{ {
unsigned int curr = offset; unsigned int curr = offset;
curr += get_len_or_sprintf(buf, curr, " {"); curr += get_len_or_sprintf(buf, curr, " {");
char *separator = ""; char *separator = "";
for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) { for (struct riscv_debug_reg_field_list list; get_next; get_next = list.get_next) {
list = get_next(context); list = get_next(context);
uint64_t field_value = riscv_debug_reg_field_value(list.field, value); uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
@@ -89,12 +89,12 @@ static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
} }
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value, struct riscv_debug_reg_ctx context, uint64_t value,
enum riscv_debug_reg_show show) enum riscv_debug_reg_show show)
{ {
unsigned int length = 0; unsigned int length = 0;
riscv_debug_reg_info_t reg = get_riscv_debug_reg_info(reg_ordinal); struct riscv_debug_reg_info reg = get_riscv_debug_reg_info(reg_ordinal);
length += get_len_or_sprintf(buf, length, "%s=", reg.name); length += get_len_or_sprintf(buf, length, "%s=", reg.name);
length += print_number(buf, length, value); length += print_number(buf, length, value);

4
src/target/riscv/debug_reg_printer.h
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@@ -27,14 +27,14 @@ enum riscv_debug_reg_show {
* (excluding '\0'). * (excluding '\0').
* *
* Example: * Example:
* const struct riscv_debug_reg_ctx_t context = { * const struct struct riscv_debug_reg_ctx context = {
* .abits = { .value = <abits value>, .is_set = true } * .abits = { .value = <abits value>, .is_set = true }
* }; * };
* char buf[riscv_debug_reg_to_s(NULL, DTM_DMI_ORDINAL, context, <dmi value>) + 1] * char buf[riscv_debug_reg_to_s(NULL, DTM_DMI_ORDINAL, context, <dmi value>) + 1]
* riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, <dmi value>); * riscv_debug_reg_to_s(buf, DTM_DMI_ORDINAL, context, <dmi value>);
*/ */
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal, unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value, struct riscv_debug_reg_ctx context, uint64_t value,
enum riscv_debug_reg_show show); enum riscv_debug_reg_show show);
#endif /* OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H */ #endif /* OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H */

8
src/target/riscv/riscv-013.c
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@@ -349,15 +349,15 @@ static void riscv013_dm_free(struct target *target)
info->dm = NULL; info->dm = NULL;
} }
static riscv_debug_reg_ctx_t get_riscv_debug_reg_ctx(const struct target *target) static struct riscv_debug_reg_ctx get_riscv_debug_reg_ctx(const struct target *target)
{ {
if (!target_was_examined(target)) { if (!target_was_examined(target)) {
const riscv_debug_reg_ctx_t default_context = {0}; const struct riscv_debug_reg_ctx default_context = {0};
return default_context; return default_context;
} }
RISCV013_INFO(info); RISCV013_INFO(info);
const riscv_debug_reg_ctx_t context = { const struct riscv_debug_reg_ctx context = {
.XLEN = { .value = riscv_xlen(target), .is_set = true }, .XLEN = { .value = riscv_xlen(target), .is_set = true },
.DXLEN = { .value = riscv_xlen(target), .is_set = true }, .DXLEN = { .value = riscv_xlen(target), .is_set = true },
.abits = { .value = info->abits, .is_set = true }, .abits = { .value = info->abits, .is_set = true },
@@ -370,7 +370,7 @@ static void log_debug_reg(struct target *target, enum riscv_debug_reg_ordinal re
{ {
if (debug_level < LOG_LVL_DEBUG) if (debug_level < LOG_LVL_DEBUG)
return; return;
const riscv_debug_reg_ctx_t context = get_riscv_debug_reg_ctx(target); const struct riscv_debug_reg_ctx context = get_riscv_debug_reg_ctx(target);
char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1); char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1);
if (!buf) { if (!buf) {
LOG_ERROR("Unable to allocate memory."); LOG_ERROR("Unable to allocate memory.");