auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

target: riscv: Sync with the RISC-V fork

Browse Source 
Regenerate autogenerated debug_defines.{c,h} files from current
riscv-debug-spec, sync remaining RISC-V target files with the
RISC-V fork.

This is based on the work of (in alphabetic order):

Aleksey Lotosh <lotosh@gmail.com>
Alexander Rumyantsev <cetygamer@gmail.com>
Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Bernhard Rosenkränzer <bero@baylibre.com>
bluew <bluewww@users.noreply.github.com>
Carsten Gosvig <40368726+cgsfv@users.noreply.github.com>
cgsfv <cgsfv@users.noreply.github.com>
Craig Blackmore <craig.blackmore@embecosm.com>
Dan Robertson <danlrobertson89@gmail.com>
Darius Rad <darius@bluespec.com>
dave-estes-syzexion <53795406+dave-estes-syzexion@users.noreply.github.com>
Dmitry Ryzhov <dmitry.ryzhov@cloudbear.ru>
Dolu1990 <charles.papon.90@gmail.com>
Emmanuel Blot <emmanuel.blot@free.fr>
Ernie Edgar <43148441+ernie-sifive@users.noreply.github.com>
Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Farid Khaydari <f.khaydari@syntacore.com>
Gleb Gagarin <gleb@sifive.com>
Greg Savin <43152568+SiFiveGregS@users.noreply.github.com>
Hang Xu <xuhang@eswincomputing.com>
Hsiangkai <Hsiangkai@gmail.com>
Jan Matyas <jan.matyas@codasip.com>
jhjung81 <48940114+jhjung81@users.noreply.github.com>
Jiuyang Liu <liu@jiuyang.me>
Kaspar Schleiser <kaspar@schleiser.de>
Khem Raj <raj.khem@gmail.com>
Kirill Radkin <kirill.radkin@syntacore.com>
liangzhen <zhen.liang@spacemit.com>
Liviu Ionescu <ilg@livius.net>
Marc Schink <openocd-dev@marcschink.de>
Megan Wachs <megan@sifive.com>
Nils Wistoff <git@wistoff.net>
Palmer Dabbelt <palmer@dabbelt.com>
panciyan <panciyan@eswincomputing.com>
Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
Paul George <command.paul@gmail.com>
Pavel S. Smirnov <Paul.Smirnov.aka.sps@gmail.com>
Philipp Wagner <mail@philipp-wagner.com>
Ryan Macdonald <rmac@sifive.com>
Samuel Obuch <samuel.obuch17@gmail.com>
Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tim Newsome <tim@casualhacker.net>
Tobias Kaiser <mail@tb-kaiser.de>
Tom Hebb <tommyhebb@gmail.com>
Tommy Murphy <tommy_murphy@hotmail.com>
wxjstz <wxjstz@126.com>
wzgpeter <wzgpeter@outlook.com>
Xiang W <wxjstz@126.com>
zhusonghe <zhusonghe@eswincomputing.com>

Checkpatch-ignore MULTISTATEMENT_MACRO_USE_DO_WHILE is added to allow a
macro in riscv-013.c that can't use do/while because it expands to a
"case ...:" statement.

Checkpatch-ignore TRAILING_SEMICOLON is added to allow a construct in
riscv-013.c where a macro expands to either code (where it needs the
semicolon) or a member of an enum (where it needs a comma).

Checkpatch-ignore LONG_LINE_COMMENT and NEW_TYPEDEFS lines are added for
the sake of the autogenerated files from riscv-debug-spec.
All non-autogenerated files have been updated for checkpatch compliance.

Checkpatch-ignore: LONG_LINE_COMMENT
Checkpatch-ignore: NEW_TYPEDEFS
Checkpatch-ignore: MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ie594915a4d6e6f9d9dad6016b176ab76409a099a
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8893
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Bernhard Rosenkränzer
2025-05-06 01:20:22 +02:00
committed by Tomas Vanek
parent ab22b0bf8f
commit 5754aebc49
29 changed files with 16775 additions and 6857 deletions
Download Patch File Download Diff File Expand all files Collapse all files

109
src/target/riscv/debug_reg_printer.c Normal file
View File

@@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include <stdio.h>
#include <inttypes.h>
#include <assert.h>
#include <stdarg.h>
#include "debug_reg_printer.h"
static unsigned int get_len_or_sprintf(char *buf, unsigned int curr, const char *format, ...)
{
assert(format);
va_list args;
int length;
va_start(args, format);
if (buf)
length = vsprintf(buf + curr, format, args);
else
length = vsnprintf(NULL, 0, format, args);
va_end(args);
assert(length >= 0);
return (unsigned int)length;
}
static unsigned int print_number(char *buf, unsigned int offset, uint64_t value)
{
const char * const format = value > 9 ? "0x%" PRIx64 : "%" PRIx64;
return get_len_or_sprintf(buf, offset, format, value);
}
static unsigned int riscv_debug_reg_field_value_to_s(char *buf, unsigned int offset,
const char * const *field_value_names, uint64_t field_value)
{
const char * const field_value_name = field_value_names ?
field_value_names[field_value] :
NULL;
if (!field_value_name)
return print_number(buf, offset, field_value);
return get_len_or_sprintf(buf, offset, "%s", field_value_name);
}
static unsigned int riscv_debug_reg_field_to_s(char *buf, unsigned int offset,
riscv_debug_reg_field_info_t field, riscv_debug_reg_ctx_t context,
uint64_t field_value)
{
const unsigned int name_len = get_len_or_sprintf(buf, offset, "%s=", field.name);
return name_len + riscv_debug_reg_field_value_to_s(buf, offset + name_len,
field.values, field_value);
}
static uint64_t riscv_debug_reg_field_value(riscv_debug_reg_field_info_t field, uint64_t value)
{
assert(field.msb < 64);
assert(field.msb >= field.lsb);
const uint64_t trailing_ones_mask = (uint64_t)(-1) >> (63 - field.msb);
return (value & trailing_ones_mask) >> field.lsb;
}
static unsigned int riscv_debug_reg_fields_to_s(char *buf, unsigned int offset,
struct riscv_debug_reg_field_list_t (*get_next)(riscv_debug_reg_ctx_t contex),
riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show)
{
unsigned int curr = offset;
curr += get_len_or_sprintf(buf, curr, " {");
char *separator = "";
for (struct riscv_debug_reg_field_list_t list; get_next; get_next = list.get_next) {
list = get_next(context);
uint64_t field_value = riscv_debug_reg_field_value(list.field, value);
if (show == RISCV_DEBUG_REG_SHOW_ALL ||
(show == RISCV_DEBUG_REG_HIDE_UNNAMED_0 &&
(field_value != 0 ||
(list.field.values && list.field.values[0]))) ||
(show == RISCV_DEBUG_REG_HIDE_ALL_0 && field_value != 0)) {
curr += get_len_or_sprintf(buf, curr, separator);
curr += riscv_debug_reg_field_to_s(buf, curr, list.field, context,
field_value);
separator = " ";
}
}
curr += get_len_or_sprintf(buf, curr, "}");
return curr - offset;
}
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show)
{
unsigned int length = 0;
riscv_debug_reg_info_t reg = get_riscv_debug_reg_info(reg_ordinal);
length += get_len_or_sprintf(buf, length, "%s=", reg.name);
length += print_number(buf, length, value);
if (reg.get_fields_head)
length += riscv_debug_reg_fields_to_s(buf, length,
reg.get_fields_head, context, value, show);
if (buf)
buf[length] = '\0';
return length;
}