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target/armv8: Handle instruction cache invalidate

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Some armv8 target have separate i-cache and d-cache.
The actual code only handles the flush of the d-cache.

Change-Id: I61a223b43c71646bbbed8fa63825360c67700988
Signed-off-by: Adrien Grassein <agrassein@nanoxplore.com>
Signed-off-by: Adrien Charruel <acharruel@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8655
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
Adrien Grassein
2024-01-18 11:58:38 +01:00
committed by Antonio Borneo
parent 98e34fd1f1
commit 5773ff9d82
4 changed files with 68 additions and 0 deletions
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2
src/target/armv8_opcodes.c
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@@ -41,6 +41,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0),
[ARMV8_OPC_STRD_IP] = ARMV8_STRD_IP(1, 0),
[ARMV8_OPC_ICIALLU] = ARMV8_SYS(SYSTEM_ICIALLU, 0x1F),
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
@@ -68,6 +69,7 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP_T3(1, 0),
[ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP_T3(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP_T3(1, 0),
[ARMV8_OPC_ICIALLU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 0),
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)