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pld: give devices a name for referencing in scripts

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Change-Id: I05e8596ffacdb6cd8da4dd8a40bb460183f4930a
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7728
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Daniel Anselmi
2023-06-03 20:16:19 +02:00
committed by Antonio Borneo
parent 7335fbdbda
commit 5ae0264055
27 changed files with 298 additions and 251 deletions
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tcl/cpld/xilinx-xc6s.cfg
+1 -1
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@@ -25,7 +25,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
-expected-id 0x0401D093 \
-expected-id 0x0403D093
pld device virtex2 $_CHIPNAME.tap
pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
set XC6S_CFG_IN 0x05
set XC6S_JSHUTDOWN 0x0d
tcl/cpld/xilinx-xc7.cfg
+1 -1
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@@ -49,7 +49,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
#jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
pld device virtex2 $_CHIPNAME.tap 1
pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b
tcl/cpld/xilinx-xcu.cfg
+1 -1
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@@ -54,7 +54,7 @@ set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
pld device virtex2 $_CHIPNAME.tap 1
pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
set XCU_JSHUTDOWN 0x0d
set XCU_JPROGRAM 0x0b
tcl/fpga/altera-arriaii.cfg
+1 -1
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@@ -28,4 +28,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x025030dd -expected-id 0x024820dd \
-expected-id 0x025140dd
pld device intel $_CHIPNAME.tap arriaii
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
tcl/fpga/altera-cycloneiii.cfg
+1 -1
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@@ -32,4 +32,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x027000dd -expected-id 0x027030dd \
-expected-id 0x027020dd
pld device intel $_CHIPNAME.tap cycloneiii
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
tcl/fpga/altera-cycloneiv.cfg
+1 -1
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@@ -38,4 +38,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x028030dd -expected-id 0x028140dd \
-expected-id 0x028040dd
pld device intel $_CHIPNAME.tap cycloneiv
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
tcl/fpga/altera-cyclonev.cfg
+1 -1
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@@ -44,4 +44,4 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x02d110dd -expected-id 0x02d010dd \
-expected-id 0x02d120dd -expected-id 0x02d020dd
pld device intel $_CHIPNAME.tap cyclonev
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
tcl/fpga/efinix_titanium.cfg
+1 -1
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@@ -20,4 +20,4 @@ jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
-expected-id 0x00680A79 \
-expected-id 0x00684A79
pld device efinix $_CHIPNAME.tap
pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
tcl/fpga/efinix_trion.cfg
+1 -1
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@@ -14,4 +14,4 @@ jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
-expected-id 0x00240A79 \
-expected-id 0x00220A79
pld device efinix $_CHIPNAME.tap
pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap
tcl/fpga/gatemate.cfg
+1 -1
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@@ -13,4 +13,4 @@ if { [info exists CHIPNAME] } {
jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
-expected-id 0x20000001
pld device gatemate $_CHIPNAME.tap
pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap
tcl/fpga/gowin_gw1n.cfg
+1 -1
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@@ -26,4 +26,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \
-expected-id 0x1100181B \
-expected-id 0x0100481B
pld device gowin $_CHIPNAME.tap
pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap
tcl/fpga/lattice_certus.cfg
+1 -1
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@@ -15,4 +15,4 @@ if { [info exists CHIPNAME] } {
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
-expected-id 0x310F1043 -expected-id 0x310F0043
pld device lattice $_CHIPNAME.tap
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
tcl/fpga/lattice_certuspro.cfg
+1 -1
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@@ -15,4 +15,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
-expected-id 0x010f4043
# -expected-id 0x01112043
pld device lattice $_CHIPNAME.tap
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
tcl/fpga/lattice_ecp2.cfg
+1 -1
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@@ -28,4 +28,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 \
-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \
-expected-id 0x01273043 -expected-id 0x01275043
pld device lattice $_CHIPNAME.tap
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
tcl/fpga/lattice_ecp3.cfg
+1 -1
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@@ -19,4 +19,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 \
-expected-id 0x01010043 -expected-id 0x01012043 \
-expected-id 0x01014043 -expected-id 0x01015043
pld device lattice $_CHIPNAME.tap
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
tcl/fpga/lattice_ecp5.cfg
+1 -1
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@@ -27,4 +27,4 @@ jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
-expected-id 0x81113043
pld device lattice $_CHIPNAME.tap
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
tcl/target/zynq_7000.cfg
+1 -1
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@@ -46,7 +46,7 @@ adapter speed 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
pld device virtex2 zynq_pl.bs 1
pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
set XC7_JSHUTDOWN 0x0d
set XC7_JPROGRAM 0x0b