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aarch64: fix software breakpoints when in aarch32 state

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Use the correct opcode for Aarch32 state, both for the breakpoint
instruction itself and the cache handling functions.

Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3981
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Matthias Welwarsky
2016-10-26 17:32:43 +02:00
committed by Paul Fertser
parent 7c85165bc1
commit 5d00fd9d1d
5 changed files with 31 additions and 6 deletions
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8
src/target/armv8_opcodes.c
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@@ -38,6 +38,10 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCPS] = ARMV8_DCPS(0, 11),
[ARMV8_OPC_DRPS] = ARMV8_DRPS,
[ARMV8_OPC_ISB_SY] = ARMV8_ISB,
[ARMV8_OPC_DCCISW] = ARMV8_SYS(SYSTEM_DCCISW, 0),
[ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
[ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
[ARMV8_OPC_HLT] = ARMV8_HLT(11),
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
@@ -55,6 +59,10 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCPS] = ARMV8_DCPS_T1(0),
[ARMV8_OPC_DRPS] = ARMV8_ERET_T1,
[ARMV8_OPC_ISB_SY] = ARMV8_ISB_SY_T1,
[ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
[ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
[ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
[ARMV8_OPC_HLT] = ARMV8_HLT_A1(11),
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)