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tcl: remove trailing whitespace

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The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.

This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
	find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types TRAILING_WHITESPACE --fix-inplace -f {} \;

The patch only changes amount and position of whitespace, thus
the following commands show empty diff
	git diff -w
	git log -w -p
	git log -w --stat

Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5616
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2020-04-26 01:07:27 +02:00
parent 6d3cb807aa
commit 5df5e89cf3
29 changed files with 140 additions and 140 deletions
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20
tcl/board/at91cap7a-stk-sdram.cfg
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@@ -43,13 +43,13 @@ proc wait_state {expression} {
return
}
}
return -code 1 "Timed out"
return -code 1 "Timed out"
}
# Use a global variable here to be able to tinker interactively with
# post reset jtag frequency.
global post_reset_khz
# Danger!!!! Even 16MHz kinda works with this target, but
# Danger!!!! Even 16MHz kinda works with this target, but
# it needs to be as low as 2000kHz to be stable.
set post_reset_khz 2000
@@ -61,25 +61,25 @@ $_TARGETNAME configure -event reset-init {
mww 0xfffffd08 0xa5000001
# Enable main oscillator
mww 0xFFFFFc20 0x00000f01
wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
# Set PLLA to 96MHz
mww 0xFFFFFc28 0x20072801
wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
# Select prescaler
mww 0xFFFFFC30 0x00000004
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
# Select master clock to 48MHz
mww 0xFFFFFC30 0x00000006
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
echo "Master clock ok."
# Now that we're up and running, crank up speed!
global post_reset_khz ; adapter speed $post_reset_khz
echo "Configuring the SDRAM controller..."
# Configure EBI Chip select for SDRAM
@@ -95,7 +95,7 @@ $_TARGETNAME configure -event reset-init {
# Configure SDRAMC CR
mww 0xFFFFEA08 0xA63392F9
# NOP command
mww 0xFFFFEA00 0x1
mww 0x20000000 0
@@ -151,7 +151,7 @@ $_TARGETNAME configure -event reset-init {
#remap internal memory at address 0x0
mww 0xffffef00 0x3
echo "SDRAM configuration ok."
}