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target/arm_disassembler: add exception related disassembly

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Add ERET/HVC/SMC disassebly decoding flow, below is testing result

> mdw 0x5c 4
0x0000005c: e160006e e1400072 e1600073 ee110f10
> arm disassemble 0x5c 4
0x0000005c	0xe160006e	ERET
0x00000060	0xe1400072	HVC 0x0002
0x00000064	0xe1600073	SMC 0x0003
0x00000068	0xee110f10	MRC p15, 0x00, r0, c1, c0, 0x00
>

Change-Id: I1beccff885b5b37747edd0b2e9fb2297ce466a00
Signed-off-by: pierre Kuo <vichy.kuo@gmail.com>
Reviewed-on: http://openocd.zylin.com/2548
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
pierre Kuo
2015-02-13 11:27:52 +08:00
committed by Paul Fertser
parent e00a56bede
commit 5e005f4129
2 changed files with 39 additions and 5 deletions
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5
src/target/arm_disassembler.h
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@@ -84,9 +84,14 @@ enum arm_instruction_type {
/* Miscellaneous instructions */
ARM_CLZ,
/* Exception return instructions */
ARM_ERET,
/* Exception generating instructions */
ARM_BKPT,
ARM_SWI,
ARM_HVC,
ARM_SMC,
/* Coprocessor instructions */
ARM_CDP,