flash/nor: add support for Nuvoton NPCX4/K3 series flash
Added NPCX flash driver to support the Nuvoton NPCX4/K3 series microcontrollers. Add config file for these series. Change-Id: I0b6e128fa51146b561f422e23a98260594b1f138 Signed-off-by: Luca Hung <YCHUNG0@nuvoton.com> Signed-off-by: Mulin CHao <mlchao@nuvoton.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7794 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Luca Hung
committed by
Antonio Borneo
Antonio Borneo
parent
2839a873a3
commit
62f76b2169
@@ -1,60 +1,70 @@
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||||
0x06,0x4b,0x07,0x4a,0x19,0x78,0x01,0x33,0x00,0x20,0x1b,0x78,0x12,0x78,0x1b,0x02,
|
||||
0x43,0xea,0x01,0x43,0x13,0x43,0x23,0x60,0x10,0xbd,0x00,0xbf,0x1a,0x00,0x02,0x40,
|
||||
0x1c,0x00,0x02,0x40,0x08,0xb5,0x14,0x22,0x00,0x21,0x00,0xf0,0x41,0xf8,0x00,0x20,
|
||||
0x08,0xbd,0x00,0x00,0x73,0xb5,0x1c,0x48,0x1b,0x4e,0x1c,0x4d,0xff,0xf7,0xf2,0xff,
|
||||
0x34,0x46,0x33,0x69,0x00,0x2b,0xfc,0xd0,0xf3,0x68,0x01,0x3b,0x03,0x2b,0x29,0xd8,
|
||||
0xdf,0xe8,0x03,0xf0,0x02,0x17,0x1f,0x22,0x01,0xa8,0xff,0xf7,0xc9,0xff,0xb0,0xb9,
|
||||
0x01,0x9b,0x2b,0x70,0x19,0x0a,0x1b,0x0c,0x69,0x70,0xab,0x70,0xe8,0x70,0x23,0x7c,
|
||||
0x00,0x23,0x23,0x74,0x62,0x7c,0x63,0x74,0xa2,0x7c,0xa3,0x74,0xe2,0x7c,0xe3,0x74,
|
||||
0xdf,0xe7,0x60,0x68,0xa1,0x68,0xff,0xf7,0x65,0xff,0x00,0x28,0xef,0xd0,0x20,0x61,
|
||||
0xfe,0xe7,0xff,0xf7,0x9b,0xff,0xf8,0xe7,0x60,0x68,0xa1,0x68,0x2a,0x46,0xff,0xf7,
|
||||
0x1b,0xff,0xf2,0xe7,0x01,0x20,0xf2,0xe7,0x00,0x00,0x0c,0x20,0x14,0x00,0x0c,0x20,
|
||||
0xf0,0xb5,0x83,0x07,0x47,0xd0,0x54,0x1e,0x00,0x2a,0x41,0xd0,0x0d,0x06,0x2d,0x0e,
|
||||
0x02,0x00,0x03,0x26,0x02,0xe0,0x1a,0x00,0x01,0x3c,0x39,0xd3,0x53,0x1c,0x15,0x70,
|
||||
0x33,0x42,0xf8,0xd1,0x03,0x2c,0x2a,0xd9,0xff,0x22,0x0a,0x40,0x15,0x02,0x15,0x43,
|
||||
0x2a,0x04,0x15,0x43,0x0f,0x2c,0x14,0xd9,0x27,0x00,0x1a,0x00,0x10,0x3f,0x3e,0x09,
|
||||
0x01,0x36,0x36,0x01,0x9e,0x19,0x15,0x60,0x55,0x60,0x95,0x60,0xd5,0x60,0x10,0x32,
|
||||
0x96,0x42,0xf8,0xd1,0x0f,0x22,0x97,0x43,0x10,0x37,0xdb,0x19,0x14,0x40,0x03,0x2c,
|
||||
0x0d,0xd9,0x1a,0x00,0x27,0x1f,0xbe,0x08,0x01,0x36,0xb6,0x00,0x9e,0x19,0x20,0xc2,
|
||||
0xb2,0x42,0xfc,0xd1,0x03,0x22,0x97,0x43,0x04,0x37,0xdb,0x19,0x14,0x40,0x00,0x2c,
|
||||
0x06,0xd0,0x09,0x06,0x1c,0x19,0x09,0x0e,0x19,0x70,0x01,0x33,0x9c,0x42,0xfb,0xd1,
|
||||
0xf0,0xbc,0x02,0xbc,0x08,0x47,0x14,0x00,0x03,0x00,0xc3,0xe7,
|
||||
|
||||
@@ -10,9 +10,29 @@
|
||||
#include <string.h>
|
||||
#include "npcx_flash.h"
|
||||
|
||||
/* flashloader parameter structure */
|
||||
__attribute__ ((section(".buffers.g_cfg")))
|
||||
static volatile struct npcx_flash_params g_cfg;
|
||||
/* data buffer */
|
||||
__attribute__ ((section(".buffers.g_buf")))
|
||||
static uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* NPCX flash driver
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void flash_init(void)
|
||||
{
|
||||
if (g_cfg.fiu_ver == NPCX_FIU_NPCK) {
|
||||
/* Set pinmux to SHD flash */
|
||||
NPCX_DEVCNT = 0x80;
|
||||
NPCX_DEVALT(0) = 0xC0;
|
||||
NPCX_DEVALT(4) = 0x00;
|
||||
} else {
|
||||
/* Avoid F_CS0 toggles while programming the internal flash. */
|
||||
NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
|
||||
}
|
||||
}
|
||||
|
||||
static void flash_execute_cmd(uint8_t code, uint8_t cts)
|
||||
{
|
||||
/* Set UMA code */
|
||||
@@ -26,11 +46,26 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts)
|
||||
|
||||
static void flash_cs_level(uint8_t level)
|
||||
{
|
||||
int sw_cs = 0;
|
||||
|
||||
if (g_cfg.fiu_ver == NPCX_FIU_NPCX) {
|
||||
sw_cs = 1;
|
||||
} else if (g_cfg.fiu_ver == NPCX_FIU_NPCX_V2) {
|
||||
sw_cs = 0;
|
||||
} else if (g_cfg.fiu_ver == NPCX_FIU_NPCK) {
|
||||
sw_cs = 1;
|
||||
/* Unlock UMA before pulling down CS in NPCK series */
|
||||
if (level)
|
||||
NPCX_CLEAR_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK);
|
||||
else
|
||||
NPCX_SET_BIT(NPCX_FIU_MSR_IE_CFG, NPCX_FIU_MSR_IE_CFG_UMA_BLOCK);
|
||||
}
|
||||
|
||||
/* Program chip select pin to high/low level */
|
||||
if (level)
|
||||
NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
|
||||
NPCX_SET_BIT(NPCX_UMA_ECTS, sw_cs);
|
||||
else
|
||||
NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
|
||||
NPCX_CLEAR_BIT(NPCX_UMA_ECTS, sw_cs);
|
||||
}
|
||||
|
||||
static void flash_set_address(uint32_t dest_addr)
|
||||
@@ -38,15 +73,15 @@ static void flash_set_address(uint32_t dest_addr)
|
||||
uint8_t *addr = (uint8_t *)&dest_addr;
|
||||
|
||||
/* Set target flash address */
|
||||
NPCX_UMA_AB2 = addr[2];
|
||||
NPCX_UMA_AB1 = addr[1];
|
||||
NPCX_UMA_AB0 = addr[0];
|
||||
NPCX_UMA_DB0 = addr[2];
|
||||
NPCX_UMA_DB1 = addr[1];
|
||||
NPCX_UMA_DB2 = addr[0];
|
||||
}
|
||||
|
||||
void delay(uint32_t i)
|
||||
static void delay(uint32_t i)
|
||||
{
|
||||
while (i--)
|
||||
;
|
||||
__asm__ volatile ("nop");
|
||||
}
|
||||
|
||||
static int flash_wait_ready(uint32_t timeout)
|
||||
@@ -104,7 +139,7 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes,
|
||||
/* Set write address */
|
||||
flash_set_address(dest_addr);
|
||||
/* Start programming */
|
||||
flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR);
|
||||
flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_3BYTE);
|
||||
for (uint32_t i = 0; i < bytes; i++) {
|
||||
flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY);
|
||||
data++;
|
||||
@@ -114,6 +149,15 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t bytes,
|
||||
flash_cs_level(1);
|
||||
}
|
||||
|
||||
static void flash_get_stsreg(uint8_t *reg1, uint8_t *reg2)
|
||||
{
|
||||
/* Read status register 1/2 for checking */
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
|
||||
*reg1 = NPCX_UMA_DB0;
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
|
||||
*reg2 = NPCX_UMA_DB0;
|
||||
}
|
||||
|
||||
/* The data to write cannot cross 256 Bytes boundary */
|
||||
static int flash_program_write(uint32_t addr, uint32_t size,
|
||||
const uint8_t *data)
|
||||
@@ -126,7 +170,41 @@ static int flash_program_write(uint32_t addr, uint32_t size,
|
||||
return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
}
|
||||
|
||||
int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
|
||||
static int flash_physical_clear_stsreg(void)
|
||||
{
|
||||
int status;
|
||||
uint8_t reg1, reg2;
|
||||
|
||||
/* Read status register 1/2 for checking */
|
||||
flash_get_stsreg(®1, ®2);
|
||||
if (reg1 == 0x00 && reg2 == 0x00)
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
|
||||
/* Enable write */
|
||||
status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
NPCX_UMA_DB0 = 0x0;
|
||||
NPCX_UMA_DB1 = 0x0;
|
||||
|
||||
/* Write status register 1/2 */
|
||||
flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
|
||||
|
||||
/* Wait writing completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Read status register 1/2 for checking */
|
||||
flash_get_stsreg(®1, ®2);
|
||||
if (reg1 != 0x00 || reg2 != 0x00)
|
||||
return NPCX_FLASH_STATUS_FAILED;
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
static int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
|
||||
{
|
||||
int status;
|
||||
uint32_t trunk_start = (offset + 0xff) & ~0xff;
|
||||
@@ -135,6 +213,13 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
|
||||
uint32_t dest_addr = offset;
|
||||
uint32_t write_len = ((trunk_start - offset) > size) ? size : (trunk_start - offset);
|
||||
|
||||
/* Configure fiu and clear status registers if needed */
|
||||
flash_init();
|
||||
status = flash_physical_clear_stsreg();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
|
||||
if (write_len) {
|
||||
status = flash_program_write(dest_addr, write_len, data);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
@@ -162,8 +247,16 @@ int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_erase(uint32_t offset, uint32_t size)
|
||||
static int flash_physical_erase(uint32_t offset, uint32_t size)
|
||||
{
|
||||
/* Configure fiu */
|
||||
flash_init();
|
||||
|
||||
/* clear flash status registers */
|
||||
int status = flash_physical_clear_stsreg();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Alignment has been checked in upper layer */
|
||||
for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE,
|
||||
offset += NPCX_FLASH_ERASE_SIZE) {
|
||||
@@ -175,7 +268,7 @@ int flash_physical_erase(uint32_t offset, uint32_t size)
|
||||
/* Set erase address */
|
||||
flash_set_address(offset);
|
||||
/* Start erase */
|
||||
flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR);
|
||||
flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_WR_3BYTE);
|
||||
/* Wait erase completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
@@ -185,10 +278,18 @@ int flash_physical_erase(uint32_t offset, uint32_t size)
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_erase_all(void)
|
||||
static int flash_physical_erase_all(void)
|
||||
{
|
||||
int status;
|
||||
|
||||
/* Configure fiu and clear status register if needed */
|
||||
flash_init();
|
||||
status = flash_physical_clear_stsreg();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Enable write */
|
||||
int status = flash_write_enable();
|
||||
status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
@@ -203,37 +304,10 @@ int flash_physical_erase_all(void)
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_physical_clear_stsreg(void)
|
||||
static int flash_get_id(uint32_t *id)
|
||||
{
|
||||
/* Enable write */
|
||||
int status = flash_write_enable();
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
flash_init();
|
||||
|
||||
NPCX_UMA_DB0 = 0x0;
|
||||
NPCX_UMA_DB1 = 0x0;
|
||||
|
||||
/* Write status register 1/2 */
|
||||
flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
|
||||
|
||||
/* Wait writing completed */
|
||||
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
|
||||
if (status != NPCX_FLASH_STATUS_OK)
|
||||
return status;
|
||||
|
||||
/* Read status register 1/2 for checking */
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
|
||||
if (NPCX_UMA_DB0 != 0x00)
|
||||
return NPCX_FLASH_STATUS_FAILED;
|
||||
flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
|
||||
if (NPCX_UMA_DB0 != 0x00)
|
||||
return NPCX_FLASH_STATUS_FAILED;
|
||||
|
||||
return NPCX_FLASH_STATUS_OK;
|
||||
}
|
||||
|
||||
int flash_get_id(uint32_t *id)
|
||||
{
|
||||
flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE);
|
||||
*id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2;
|
||||
|
||||
@@ -243,7 +317,7 @@ int flash_get_id(uint32_t *id)
|
||||
/*----------------------------------------------------------------------------
|
||||
* flash loader function
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t flashloader_init(struct npcx_flash_params *params)
|
||||
static uint32_t flashloader_init(struct npcx_flash_params *params)
|
||||
{
|
||||
/* Initialize params buffers */
|
||||
memset(params, 0, sizeof(struct npcx_flash_params));
|
||||
@@ -254,30 +328,13 @@ uint32_t flashloader_init(struct npcx_flash_params *params)
|
||||
/*----------------------------------------------------------------------------
|
||||
* Functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* flashloader parameter structure */
|
||||
__attribute__ ((section(".buffers.g_cfg")))
|
||||
volatile struct npcx_flash_params g_cfg;
|
||||
/* data buffer */
|
||||
__attribute__ ((section(".buffers.g_buf")))
|
||||
uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
|
||||
|
||||
int main(void)
|
||||
static int main(void)
|
||||
{
|
||||
uint32_t id;
|
||||
uint32_t id, status;
|
||||
|
||||
/* set buffer */
|
||||
flashloader_init((struct npcx_flash_params *)&g_cfg);
|
||||
|
||||
/* Avoid F_CS0 toggles while programming the internal flash. */
|
||||
NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
|
||||
|
||||
/* clear flash status registers */
|
||||
int status = flash_physical_clear_stsreg();
|
||||
if (status != NPCX_FLASH_STATUS_OK) {
|
||||
while (1)
|
||||
g_cfg.sync = status;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
/* wait command*/
|
||||
while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT)
|
||||
|
||||
@@ -80,6 +80,7 @@
|
||||
#define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032)
|
||||
#define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033)
|
||||
#define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034)
|
||||
#define NPCX_FIU_MSR_IE_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x043)
|
||||
|
||||
/* FIU register fields */
|
||||
#define NPCX_RESP_CFG_IAD_EN 0
|
||||
@@ -93,6 +94,7 @@
|
||||
#define NPCX_UMA_ECTS_SW_CS1 1
|
||||
#define NPCX_UMA_ECTS_SEC_CS 2
|
||||
#define NPCX_UMA_ECTS_UMA_LOCK 3
|
||||
#define NPCX_FIU_MSR_IE_CFG_UMA_BLOCK 3
|
||||
|
||||
/* Flash UMA commands for npcx internal SPI flash */
|
||||
#define NPCX_CMD_READ_ID 0x9F
|
||||
@@ -130,7 +132,6 @@
|
||||
#define NPCX_SPI_FLASH_SR1_BUSY (1 << 0)
|
||||
|
||||
#define NPCX_MASK_CMD_ONLY (0xC0)
|
||||
#define NPCX_MASK_CMD_ADR (0xC0 | 0x08)
|
||||
#define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01)
|
||||
#define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01)
|
||||
#define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02)
|
||||
@@ -143,10 +144,12 @@
|
||||
#define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20)
|
||||
#define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01)
|
||||
#define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02)
|
||||
#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08)
|
||||
#define NPCX_MASK_CMD_WR_3BYTE (0xC0 | 0x20 | 0x10 | 0x03)
|
||||
#define NPCX_MASK_CMD_WR_4BYTE (0xC0 | 0x20 | 0x10 | 0x04)
|
||||
|
||||
/* Flash loader parameters */
|
||||
struct __attribute__((__packed__)) npcx_flash_params {
|
||||
uint32_t fiu_ver; /* Flash controller unit version */
|
||||
uint32_t addr; /* Address in flash */
|
||||
uint32_t len; /* Number of bytes */
|
||||
uint32_t cmd; /* Command */
|
||||
@@ -176,4 +179,10 @@ enum npcx_flash_status {
|
||||
NPCX_FLASH_STATUS_FAILED_TIMEOUT,
|
||||
};
|
||||
|
||||
enum npcx_fiu_ver {
|
||||
NPCX_FIU_NPCX = 0,
|
||||
NPCX_FIU_NPCX_V2,
|
||||
NPCX_FIU_NPCK,
|
||||
};
|
||||
|
||||
#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
/* NPCX flash loader information */
|
||||
#define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000
|
||||
#define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR
|
||||
#define NPCX_FLASH_LOADER_PARAMS_SIZE 16
|
||||
#define NPCX_FLASH_LOADER_PARAMS_SIZE 20
|
||||
#define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR + NPCX_FLASH_LOADER_PARAMS_SIZE)
|
||||
#define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE
|
||||
#define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR + NPCX_FLASH_LOADER_BUFFER_SIZE)
|
||||
|
||||
Reference in New Issue
Block a user