jtag: drivers: xlnx-pcie-xvc: Add support for SWD mode.
Add support for SWD debug to the Xilinx XVC/PCIe driver. This is possible since the device is essentially a shift-register. So doing SWD vs JTAG is a matter of wiring things correctly on the RTL side (use TMS for SWDI, TDO for SWDO). The clang static checker doesn't find any new problems with this change. Change-Id: I3959e21440cd1036769e8e56a55e601d3e4aee9a Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: http://openocd.zylin.com/5447 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Moritz Fischer
committed by
Antonio Borneo
Antonio Borneo
parent
057aed11a2
commit
64733434e2
@@ -37,6 +37,9 @@
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#define XLNX_XVC_VSEC_ID 0x8
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#define XLNX_XVC_MAX_BITS 0x20
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#define MASK_ACK(x) (((x) >> 9) & 0x7)
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#define MASK_PAR(x) ((int)((x) & 0x1))
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struct xlnx_pcie_xvc {
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int fd;
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unsigned offset;
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@@ -471,17 +474,224 @@ static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
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COMMAND_REGISTRATION_DONE
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};
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static struct jtag_interface xlnx_pcie_xvc_interface = {
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static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
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.execute_queue = &xlnx_pcie_xvc_execute_queue,
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};
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static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
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{
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size_t left, write;
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uint32_t send;
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int err;
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left = length;
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while (left) {
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write = MIN(XLNX_XVC_MAX_BITS, left);
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send = buf_get_u32(seq, 0, write);
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err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
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if (err != ERROR_OK)
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return err;
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left -= write;
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seq += sizeof(uint32_t);
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};
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
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{
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switch (seq) {
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case LINE_RESET:
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LOG_DEBUG("SWD line reset");
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return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
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swd_seq_line_reset_len);
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case JTAG_TO_SWD:
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LOG_DEBUG("JTAG-to-SWD");
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return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
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swd_seq_jtag_to_swd_len);
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case SWD_TO_JTAG:
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LOG_DEBUG("SWD-to-JTAG");
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return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
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swd_seq_swd_to_jtag_len);
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default:
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LOG_ERROR("Sequence %d not supported", seq);
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static int queued_retval;
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static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
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uint32_t ap_delay_clk);
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static void swd_clear_sticky_errors(void)
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{
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xlnx_pcie_xvc_swd_write_reg(swd_cmd(false, false, DP_ABORT),
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STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
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}
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static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
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uint32_t ap_delay_clk)
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{
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uint32_t res, ack, rpar;
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int err;
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assert(cmd & SWD_CMD_RnW);
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cmd |= SWD_CMD_START | SWD_CMD_PARK;
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/* cmd + ack */
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err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
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if (err != ERROR_OK)
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goto err_out;
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ack = MASK_ACK(res);
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/* read data */
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err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
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if (err != ERROR_OK)
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goto err_out;
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/* parity + trn */
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err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
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if (err != ERROR_OK)
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goto err_out;
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LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
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ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
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"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
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cmd & SWD_CMD_APnDP ? "AP" : "DP",
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cmd & SWD_CMD_RnW ? "read" : "write",
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(cmd & SWD_CMD_A32) >> 1,
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res);
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switch (ack) {
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case SWD_ACK_OK:
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if (MASK_PAR(rpar) != parity_u32(res)) {
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LOG_DEBUG_IO("Wrong parity detected");
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queued_retval = ERROR_FAIL;
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return;
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}
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if (value)
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*value = res;
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if (cmd & SWD_CMD_APnDP)
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err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
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queued_retval = err;
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return;
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case SWD_ACK_WAIT:
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LOG_DEBUG_IO("SWD_ACK_WAIT");
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swd_clear_sticky_errors();
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return;
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case SWD_ACK_FAULT:
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LOG_DEBUG_IO("SWD_ACK_FAULT");
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queued_retval = ack;
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return;
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default:
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LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
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queued_retval = ack;
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return;
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}
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err_out:
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queued_retval = err;
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}
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static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
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uint32_t ap_delay_clk)
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{
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uint32_t res, ack;
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int err;
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assert(!(cmd & SWD_CMD_RnW));
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cmd |= SWD_CMD_START | SWD_CMD_PARK;
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/* cmd + trn + ack */
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err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
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if (err != ERROR_OK)
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goto err_out;
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ack = MASK_ACK(res);
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/* write data */
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err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
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if (err != ERROR_OK)
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goto err_out;
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/* parity + trn */
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err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
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if (err != ERROR_OK)
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goto err_out;
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LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
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ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
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"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
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cmd & SWD_CMD_APnDP ? "AP" : "DP",
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cmd & SWD_CMD_RnW ? "read" : "write",
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(cmd & SWD_CMD_A32) >> 1,
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value);
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switch (ack) {
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case SWD_ACK_OK:
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if (cmd & SWD_CMD_APnDP)
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err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
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queued_retval = err;
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return;
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case SWD_ACK_WAIT:
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LOG_DEBUG_IO("SWD_ACK_WAIT");
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swd_clear_sticky_errors();
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return;
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case SWD_ACK_FAULT:
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LOG_DEBUG_IO("SWD_ACK_FAULT");
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queued_retval = ack;
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return;
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default:
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LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
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queued_retval = ack;
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return;
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}
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err_out:
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queued_retval = err;
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}
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static int xlnx_pcie_xvc_swd_run_queue(void)
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{
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int err;
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/* we want at least 8 idle cycles between each transaction */
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err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
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if (err != ERROR_OK)
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return err;
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err = queued_retval;
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queued_retval = ERROR_OK;
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LOG_DEBUG("SWD queue return value: %02x", err);
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return err;
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}
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static int xlnx_pcie_xvc_swd_init(void)
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{
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return ERROR_OK;
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}
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static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
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.init = xlnx_pcie_xvc_swd_init,
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.switch_seq = xlnx_pcie_xvc_swd_switch_seq,
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.read_reg = xlnx_pcie_xvc_swd_read_reg,
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.write_reg = xlnx_pcie_xvc_swd_write_reg,
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.run = xlnx_pcie_xvc_swd_run_queue,
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};
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static const char * const xlnx_pcie_xvc_transports[] = { "jtag", "swd", NULL };
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struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
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.name = "xlnx_pcie_xvc",
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.transports = jtag_only,
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.transports = xlnx_pcie_xvc_transports,
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.commands = xlnx_pcie_xvc_command_handlers,
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.init = &xlnx_pcie_xvc_init,
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.quit = &xlnx_pcie_xvc_quit,
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.jtag_ops = &xlnx_pcie_xvc_interface,
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.jtag_ops = &xlnx_pcie_xvc_jtag_ops,
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.swd_ops = &xlnx_pcie_xvc_swd_ops,
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};
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