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tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 18:28:52 +02:00
parent f855fdcf0d
commit 64d89d5ee1
33 changed files with 109 additions and 109 deletions
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16
tcl/board/icnova_sam9g45_sodimm.cfg
View File

@@ -89,27 +89,27 @@ proc at91sam9g45_init { } {
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
#mww 0xfffffc28 0x202a3f01
mww 0xfffffc28 0x20c73f03
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert.
#mww 0xfffffc30 0x00000101
mww 0xfffffc30 0x00001301
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz
@@ -214,7 +214,7 @@ proc at91sam9g45_init { } {
sleep 1
# 9. Enable DLL Reset (set DLL bit)
set CR [expr [read_register 0xffffe608] | 0x80]
set CR [expr {[read_register 0xffffe608] | 0x80}]
mww 0xffffe608 $CR
# 10. mode register cycle to reset the DLL
@@ -236,7 +236,7 @@ proc at91sam9g45_init { } {
# 12.3 delay 10 cycles
# 13. disable DLL reset (clear DLL bit)
set CR [expr [read_register 0xffffe608] & 0xffffff7f]
set CR [expr {[read_register 0xffffe608] & 0xffffff7f}]
mww 0xffffe608 $CR
# 14. mode register set cycle
@@ -244,7 +244,7 @@ proc at91sam9g45_init { } {
mww 0x70000000 0x1
# 15. program OCD field (set OCD bits)
set CR [expr [read_register 0xffffe608] | 0x7000]
set CR [expr {[read_register 0xffffe608] | 0x7000}]
mww 0xffffe608 $CR
# 16. (EMRS1)
@@ -253,7 +253,7 @@ proc at91sam9g45_init { } {
# 16.1 delay 2 cycles
# 17. disable OCD field (clear OCD bits)
set CR [expr [read_register 0xffffe608] & 0xffff8fff]
set CR [expr {[read_register 0xffffe608] & 0xffff8fff}]
mww 0xffffe608 $CR
# 18. (EMRS1)