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tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 18:28:52 +02:00
parent f855fdcf0d
commit 64d89d5ee1
33 changed files with 109 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
tcl/target/am335x.cfg
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@@ -103,10 +103,10 @@ proc disable_watchdog { } {
# Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs.
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
}
}
$_TARGETNAME configure -event reset-end { disable_watchdog }

14
tcl/target/am437x.cfg
View File

@@ -512,10 +512,10 @@ proc disable_watchdog { } {
# Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs.
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
}
}
@@ -725,13 +725,13 @@ proc emif_prcm_clk_enable { } {
proc vtp_enable { } {
global VTP_CTRL_REG
set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ]
set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
mww $VTP_CTRL_REG $vtp
set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ]
set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
mww $VTP_CTRL_REG $vtp
set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ]
set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
mww $VTP_CTRL_REG $vtp
}
@@ -948,7 +948,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
emif_prcm_clk_enable
vtp_enable
set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ]
set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
mww $CM_DLL_CTRL $dll
while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
@@ -978,7 +978,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
sleep 10
set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ]
set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
mww $EXT_PHY_CTRL_36 $tmp
mww $EXT_PHY_CTRL_36_SHDW $tmp

2
tcl/target/bluenrg-x.cfg
View File

@@ -65,7 +65,7 @@ $_TARGETNAME configure -event resumed {
global WDOG_VALUE_SET
set _JTAG_IDCODE [mrw 0x40000004]
if {$_JTAG_IDCODE != 0x0201E041} {
if [expr $WDOG_VALUE_SET] {
if {$WDOG_VALUE_SET} {
# Restore watchdog enable value after resume. Only Bluenrg-1/2
mww 0x40700008 $WDOG_VALUE
set WDOG_VALUE_SET 0

6
tcl/target/c100config.tcl
View File

@@ -26,14 +26,14 @@ proc configC100 {} {
dict set configC100 w_amba 1
dict set configC100 x_amba 1
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
# Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0
dict set configC100 x_arm 1
# y = arm_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
}
@@ -362,7 +362,7 @@ proc putcUART0 {char} {
# convert the 'char' to digit
set tmp [ scan $char %c ]
# /* wait for room in the tx FIFO on FFUART */
while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
mww $UART0_THR $tmp
if { $char == "\n" } { putcUART0 \r }
}

22
tcl/target/c100helper.tcl
View File

@@ -119,17 +119,17 @@ proc showAmbaClk {} {
echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
set x [expr {($value(0) & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
set y [expr {($value(0) & 0x00000007F)}]
echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
set w [expr {($value(0) & 0x000000300) >> 8}]
echo [format "w: %d" $w]
echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
@@ -177,7 +177,7 @@ proc setupAmbaClk {} {
mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
@@ -194,17 +194,17 @@ proc showArmClk {} {
echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16]
set x [expr {($value(0) & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)]
set y [expr {($value(0) & 0x00000007F)}]
echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8]
set w [expr {($value(0) & 0x000000300) >> 8}]
echo [format "w: %d" $w]
echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
@@ -251,7 +251,7 @@ proc setupArmClk {} {
mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
@@ -442,7 +442,7 @@ proc initC100 {} {
# APB init
# // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
mww [expr $APB_ACCESS_WS_REG] 0x40
mww $APB_ACCESS_WS_REG 0x40
# AHB init
# // enable all 6 masters for ARAM
mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0

12
tcl/target/davinci.cfg
View File

@@ -4,7 +4,7 @@
# davinci_pinmux: assigns PINMUX$reg <== $value
proc davinci_pinmux {soc reg value} {
mww [expr [dict get $soc sysbase] + 4 * $reg] $value
mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
}
source [find mem_helper.tcl]
@@ -110,7 +110,7 @@ proc pll_v02_setup {pll_addr mult config} {
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
}
mww [expr {$pll_addr + 0x0138}] 0x00
@@ -272,11 +272,11 @@ proc pll_v03_setup {pll_addr mult config} {
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
}
mww [expr {$pll_addr + 0x0138}] 0x00
set addr [dict get $config ctladdr]
while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 }
while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
# 12 - set PLLEN (bit 0) ... leave bypass mode
set pll_ctrl [expr {$pll_ctrl | 0x0001}]
@@ -306,13 +306,13 @@ proc psc_go {} {
set ptstat_addr [expr {$psc_addr + 0x0128}]
# just in case PTSTAT.go isn't clear
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
# write PTCMD.go ... ignoring any DSP power domain
mww [expr {$psc_addr + 0x0120}] 1
# wait for PTSTAT.go to clear (again ignoring DSP power domain)
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
}
#

4
tcl/target/hilscher_netx500.cfg
View File

@@ -36,10 +36,10 @@ proc mread32 {addr} {
proc sdram_fix { } {
set accesskey [mread32 0x00100070]
mww 0x00100070 [expr $accesskey]
mww 0x00100070 $accesskey
mww 0x0010002c 0x00000001
if {[expr [mread32 0x0010002c] & 0x07] == 0x07} {
if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} {
puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
} else {
puts "SDRAM Fix succeeded!"

4
tcl/target/icepick.cfg
View File

@@ -54,8 +54,8 @@ proc icepick_c_disconnect {jrc} {
proc icepick_c_router {jrc rw block register payload} {
set new_dr_value \
[expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ]
[expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ]
# echo "\tNew router value:\t0x[format %x $new_dr_value]"

12
tcl/target/psoc4.cfg
View File

@@ -78,18 +78,18 @@ proc psoc4_get_family_id {} {
if { $err } {
return 0
}
if { [expr $romtable_pid(0) & 0xffffff00 ]
|| [expr $romtable_pid(1) & 0xffffff00 ]
|| [expr $romtable_pid(2) & 0xffffff00 ] } {
if { [expr {$romtable_pid(0) & 0xffffff00 }]
|| [expr {$romtable_pid(1) & 0xffffff00 }]
|| [expr {$romtable_pid(2) & 0xffffff00 }] } {
echo "Unexpected data in ROMTABLE"
return 0
}
set designer_id [expr (( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) ]
set designer_id [expr {(( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) }]
if { $designer_id != 0xb4 } {
echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
return 0
}
set family_id [expr ( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) ]
set family_id [expr {( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) }]
return $family_id
}
@@ -194,7 +194,7 @@ proc ocd_process_reset_inner { MODE } {
# Set registers to reset vector values
mem2array value 32 0 2
reg pc [expr $value(1) & 0xfffffffe ]
reg pc [expr {$value(1) & 0xfffffffe} ]
reg msp $value(0)
if { $PSOC4_TEST_MODE_WORKAROUND } {

8
tcl/target/stellaris.cfg
View File

@@ -83,7 +83,7 @@ proc reset_peripherals {family} {
mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
# RCC and RCC2 to their reset values
mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
mww $SYSCTL_RCC2 0x07806810
mww $SYSCTL_RCC 0x078e3ad1
@@ -121,8 +121,8 @@ proc reset_peripherals {family} {
mww $SYSCTL_MISC 0xffffffff
# Wait for any pending flash operations to complete
while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
# Reset the flash controller registers
mww $FLASH_FMA 0
@@ -152,7 +152,7 @@ $_TARGETNAME configure -event reset-start {
if {$_DEVICECLASS != 0xff} {
set device_class $_DEVICECLASS
} else {
set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
}
if {$device_class == 0 || $device_class == 1 ||

2
tcl/target/stm32mp15x.cfg
View File

@@ -107,7 +107,7 @@ proc toggle_cpu0_dbg_claim0 {} {
proc detect_cpu1 {} {
$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
set dual_core [expr $cpu1_prsr(0) & 1]
set dual_core [expr {$cpu1_prsr(0) & 1}]
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}

4
tcl/target/u8500.cfg
View File

@@ -18,12 +18,12 @@ proc ocd_gdb_restart {target_id} {
global _TARGETNAME_1
global _SMP
targets $_TARGETNAME_1
if { [expr ($_SMP == 1)] } {
if { $_SMP == 1 } {
cortex_a smp off
}
rst_run
halt
if { [expr ($_SMP == 1)]} {
if { $_SMP == 1 } {
cortex_a smp on
}
}