From 663d97b38550bf0aba42005912822bff713caeda Mon Sep 17 00:00:00 2001 From: Ahmed BOUDJELIDA Date: Thu, 12 Dec 2024 09:44:41 +0100 Subject: [PATCH] contrib/firmware/angie: Change ANGIE IOs configuration We disconnect port B and D which are going to be used by GPIF module. Change-Id: Iffaccbb43ded4b2e0b37f5ee1cc7509e90b0f3d4 Signed-off-by: Ahmed BOUDJELIDA Reviewed-on: https://review.openocd.org/c/openocd/+/8714 Reviewed-by: Antonio Borneo Tested-by: jenkins --- contrib/firmware/angie/c/Makefile | 4 +- contrib/firmware/angie/c/include/io.h | 48 ++++++-------------- contrib/firmware/angie/c/include/reg_ezusb.h | 8 ++-- contrib/firmware/angie/c/include/usb.h | 10 +--- contrib/firmware/angie/c/src/i2c.c | 27 +++++------ 5 files changed, 34 insertions(+), 63 deletions(-) diff --git a/contrib/firmware/angie/c/Makefile b/contrib/firmware/angie/c/Makefile index 1bcc1f7d1..21873da6b 100644 --- a/contrib/firmware/angie/c/Makefile +++ b/contrib/firmware/angie/c/Makefile @@ -38,10 +38,8 @@ LDFLAGS = --code-loc 0x0000 --code-size $(CODE_SIZE) --xram-loc $(XRAM_LOC) \ --xram-size $(XRAM_SIZE) --iram-size 256 --model-small # list of base object files -OBJECTS = main.rel usb.rel protocol.rel jtag.rel delay.rel USBJmpTb.rel serial.rel gpif.rel i2c.rel +OBJECTS = main.rel usb.rel delay.rel USBJmpTb.rel gpif.rel i2c.rel serial.rel HEADERS = $(INCLUDE_DIR)/usb.h \ - $(INCLUDE_DIR)/protocol.h \ - $(INCLUDE_DIR)/jtag.h \ $(INCLUDE_DIR)/delay.h \ $(INCLUDE_DIR)/reg_ezusb.h \ $(INCLUDE_DIR)/io.h \ diff --git a/contrib/firmware/angie/c/include/io.h b/contrib/firmware/angie/c/include/io.h index 19289d11d..447aec3b4 100644 --- a/contrib/firmware/angie/c/include/io.h +++ b/contrib/firmware/angie/c/include/io.h @@ -14,44 +14,26 @@ #include "reg_ezusb.h" -/*************************************************************************** - * JTAG Signals: * - *************************************************************************** - * TMS ....... Test Mode Select * - * TCK ....... Test Clock * - * TDI ....... Test Data Input (from device point of view, not JTAG * - * adapter point of view!) * - * TDO ....... Test Data Output (from device point of view, not JTAG * - * adapter point of view!) * - * TRST ...... Test Reset: Used to reset the TAP Finite State Machine * - * into the Test Logic Reset state * - * SRST ..... Chip Reset * - ***************************************************************************/ - /* PORT A */ -/* PA0 Not Connected */ +#define PIN_SDA_DIR IOA0 /* PA1 Not Connected */ -#define PIN_RDWR_B IOA2 -#define PIN_CSI_B IOA3 -#define PIN_INIT_B IOA4 -#define PIN_PROGRAM_B IOA5 +#define PIN_RDWR_B IOA2 +#define PIN_SDA IOA3 +#define PIN_SCL IOA4 +#define PIN_PROGRAM_B IOA5 /* PA6 Not Connected */ /* PA7 Not Connected */ /* PORT B */ -#define PIN_TRST IOB0 -#define PIN_TMS IOB1 -#define PIN_TCK IOB2 -#define PIN_TDI IOB3 -#define PIN_TDO IOB4 -#define PIN_SRST IOB5 +/* PB0 Not Connected */ +/* PB1 Not Connected */ +/* PB2 Not Connected */ +/* PB3 Not Connected */ +/* PB4 Not Connected */ +/* PB5 Not Connected */ /* PB6 Not Connected */ /* PB7 Not Connected */ -/* JTAG Signals with direction 'OUT' on port B */ -/* PIN_TDI - PIN_TCK - PIN_TMS - PIN_TRST - PIN_SRST */ -#define MASK_PORTB_DIRECTION_OUT (bmbit0 | bmbit1 | bmbit2 | bmbit3 | bmbit5) - /* PORT C */ #define PIN_T0 IOC0 #define PIN_T1 IOC1 @@ -63,10 +45,10 @@ /* PC7 Not Connected */ /* PORT D */ -#define PIN_SDA IOD0 -#define PIN_SCL IOD1 -#define PIN_SDA_DIR IOD2 -#define PIN_SCL_DIR IOD3 +/* PD0 Not Connected */ +/* PD1 Not Connected */ +/* PD2 Not Connected */ +/* PD3 Not Connected */ /* PD4 Not Connected */ /* PD5 Not Connected */ /* PD6 Not Connected */ diff --git a/contrib/firmware/angie/c/include/reg_ezusb.h b/contrib/firmware/angie/c/include/reg_ezusb.h index c22476a1a..735ccaa8a 100644 --- a/contrib/firmware/angie/c/include/reg_ezusb.h +++ b/contrib/firmware/angie/c/include/reg_ezusb.h @@ -634,10 +634,10 @@ SFRX(CT4, 0xE6FE); SFRX(EP0BUF[64], 0xE740); SFRX(EP1INBUF[64], 0xE7C0); SFRX(EP1OUTBUF[64], 0xE780); -SFRX(EP2FIFOBUF[512], 0xF000); -SFRX(EP4FIFOBUF[512], 0xF400); -SFRX(EP6FIFOBUF[512], 0xF800); -SFRX(EP8FIFOBUF[512], 0xFC00); +SFRX(EP2FIFOBUF[1024], 0xF000); +SFRX(EP4FIFOBUF[1024], 0xF400); +SFRX(EP6FIFOBUF[1024], 0xF800); +SFRX(EP8FIFOBUF[1024], 0xFC00); /* Error Correction Code (ECC) Registers (FX2LP/FX1 only) */ SFRX(ECCCFG, 0xE628); diff --git a/contrib/firmware/angie/c/include/usb.h b/contrib/firmware/angie/c/include/usb.h index ad8be787e..37d3b8ae2 100644 --- a/contrib/firmware/angie/c/include/usb.h +++ b/contrib/firmware/angie/c/include/usb.h @@ -125,12 +125,6 @@ struct setup_data { uint16_t wlength; /**< Number of bytes to transfer in data stage. */ }; -/* External declarations for variables that need to be accessed outside of - * the USB module */ -extern volatile bool ep1_out; -extern volatile bool ep1_in; -extern volatile bool ep6_out; - extern volatile __xdata __at 0xE6B8 struct setup_data setup_data; /* @@ -278,8 +272,8 @@ bool usb_handle_set_feature(void); bool usb_handle_get_descriptor(void); void usb_handle_set_interface(void); void usb_handle_setup_data(void); -void usb_handle_i2c_in(void); -void usb_handle_i2c_out(void); +bool usb_handle_vcommands(void); +void set_gpif_cnt(uint32_t count); void i2c_recieve(void); void ep_init(void); diff --git a/contrib/firmware/angie/c/src/i2c.c b/contrib/firmware/angie/c/src/i2c.c index 10a463bf7..9aadc2c25 100644 --- a/contrib/firmware/angie/c/src/i2c.c +++ b/contrib/firmware/angie/c/src/i2c.c @@ -14,12 +14,11 @@ void start_cd(void) { - PIN_SCL_DIR = 0; - PIN_SDA_DIR = 0; + PIN_SDA_DIR = 0; // SP6 SDA: OUT delay_us(10); - PIN_SDA = 0; //SDA = 1; + PIN_SDA = 0; delay_us(1); - PIN_SCL = 0; //SCL = 1; + PIN_SCL = 0; delay_us(1); } @@ -43,9 +42,7 @@ void stop_cd(void) delay_us(1); PIN_SDA = 1; delay_us(1); - PIN_SDA_DIR = 1; - delay_us(1); - PIN_SCL_DIR = 1; + PIN_SDA_DIR = 1; // SP6 SDA: IN delay_us(1); } @@ -79,16 +76,16 @@ void send_nack(void) bool get_ack(void) { - PIN_SDA_DIR = 1; + PIN_SDA_DIR = 1; // SP6 SDA: IN delay_us(1); - OED = 0xFE; + OEA = 0xF7; // FX2 SDA: IN PIN_SCL = 1; delay_us(1); bool ack = PIN_SDA; PIN_SCL = 0; delay_us(1); - OED = 0xFF; - PIN_SDA_DIR = 0; + OEA = 0xFF; // FX2 SDA: OUT + PIN_SDA_DIR = 0; // SP6 SDA: OUT delay_us(1); return ack; } @@ -123,8 +120,8 @@ void send_byte(uint8_t input) uint8_t receive_byte(void) { - PIN_SDA_DIR = 1; //FX2 <-- FPGA - OED = 0xFE; + PIN_SDA_DIR = 1; // SP6 SDA: IN + OEA = 0xF7; // FX2 SDA: IN uint8_t input = 0x00; for (uint8_t i = 0; i < 8; i++) { PIN_SCL = 1; @@ -138,7 +135,7 @@ uint8_t receive_byte(void) PIN_SCL = 0; delay_us(1); } - OED = 0xFF; - PIN_SDA_DIR = 0; + OEA = 0xFF; // FX2 SDA: OUT + PIN_SDA_DIR = 0; // SP6 SDA: OUT return input; }