mips: optimize CP0 read/write code
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is possible to load the base address with a lui instruction and only one pracc access. Offsets to the pracc code addresses are defined to simplify the code and probably make it a bit more readable or self-explained. Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/951 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
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Spencer Oliver
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9aad563d15
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6644018337
@@ -30,6 +30,7 @@
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#include <target/mips_ejtag.h>
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#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000
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#define MIPS32_PRACC_BASE_ADDR 0xFF200000
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#define MIPS32_PRACC_FASTDATA_SIZE 16
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#define MIPS32_PRACC_TEXT 0xFF200200
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#define MIPS32_PRACC_STACK 0xFF204000
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@@ -38,6 +39,12 @@
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#define MIPS32_PRACC_PARAM_OUT (MIPS32_PRACC_PARAM_IN + MIPS32_PRACC_PARAM_IN_SIZE)
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#define MIPS32_PRACC_PARAM_OUT_SIZE 0x1000
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#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_TEXT_OFFSET (MIPS32_PRACC_TEXT - MIPS32_PRACC_BASE_ADDR)
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#define PRACC_IN_OFFSET (MIPS32_PRACC_PARAM_IN - MIPS32_PRACC_BASE_ADDR)
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#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
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#define PRACC_STACK_OFFSET (MIPS32_PRACC_STACK - MIPS32_PRACC_BASE_ADDR)
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#define MIPS32_FASTDATA_HANDLER_SIZE 0x80
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#define UPPER16(uint32_t) (uint32_t >> 16)
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#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
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