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armv7a: access monitor registers only with security extensions

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Accordingly to ARM DDI 0406C at B1.5, the security extensions for
armv7a are optional extensions and can be detected by reading
ID_PFR1.
The monitor mode is part of the security extensions and the shadow
registers "sp_mon", "lr_mon" and "spsr_mon" are only present with
the security extensions.

Read the register ID_PFR1 during cortex_a examine, determine if
security extension is present and then conditionally enable the
visibility of the monitor mode shadow registers.

Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5259
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2019-06-24 18:28:31 +02:00
parent 9626402c5a
commit 6900c5af4e
2 changed files with 14 additions and 2 deletions
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13
src/target/cortex_a.c
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@@ -2678,7 +2678,7 @@ static int cortex_a_examine_first(struct target *target)
int i;
int retval = ERROR_OK;
uint32_t didr, cpuid, dbg_osreg;
uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
/* Search for the APB-AP - it is needed for access to debug registers */
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
@@ -2787,7 +2787,16 @@ static int cortex_a_examine_first(struct target *target)
}
}
armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ID_PFR1, &dbg_idpfr1);
if (retval != ERROR_OK)
return retval;
if (dbg_idpfr1 & 0x000000f0) {
LOG_DEBUG("target->coreid %" PRId32 " has security extensions",
target->coreid);
armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
}
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {