aarch64: add support for "reset halt"
Support halting the CPU directly after a reset. If halt is requested, the CPU stops directly at the reset vector, before any code is executed. This functionality was implemented using the Reset Catch debug event. Change-Id: If90d54c088442340376f0b588ba10267ea8e7327 Signed-off-by: Christian Hoff <christian.hoff@advantest.com> Reviewed-on: http://openocd.zylin.com/5947 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This commit is contained in:
committed by
Antonio Borneo
parent
25218e8935
commit
6c0151623c
@@ -16,6 +16,7 @@
|
||||
#define OPENOCD_TARGET_ARMV8_DPM_H
|
||||
|
||||
#include "arm_dpm.h"
|
||||
#include "helper/bits.h"
|
||||
|
||||
/* forward-declare struct armv8_common */
|
||||
struct armv8_common;
|
||||
@@ -96,6 +97,12 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t wfar);
|
||||
#define DRCR_RESTART (1 << 1)
|
||||
#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
|
||||
|
||||
/* ECR (Execution Control Register) bits */
|
||||
#define ECR_RCE BIT(1)
|
||||
|
||||
/* ESR (Event Status Register) bits */
|
||||
#define ESR_RC BIT(1)
|
||||
|
||||
/* PRSR (processor debug status register) bits */
|
||||
#define PRSR_PU (1 << 0)
|
||||
#define PRSR_SPD (1 << 1)
|
||||
|
||||
Reference in New Issue
Block a user