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flash/stm32l4x: add support of STM32WL5x dual core

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according the RM0453, the second core  have a different Flash CR and SR
registers for flash operations (called C2CR and C2SR).
so we need to a different flash_regs than older L4 devices.
@see stm32wl_cpu2_flash_regs

the C2CR register don't contain LOCK and OPTLOCK bits, and this explain
the addition of new register index called STM32_FLASH_CR_WLK_INDEX to
look-up the CR with lock, to be used in locking/unlocking the flash.

note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
to solve this read the UID64 (IEEE 64-bit unique device ID register)

Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6050
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI
2021-02-04 22:43:52 +01:00
committed by Oleksij Rempel
parent 64fbd60787
commit 6c1e1a212a
3 changed files with 206 additions and 55 deletions
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src/flash/nor/stm32l4x.h
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@@ -83,6 +83,9 @@
#define DBGMCU_IDCODE_G0 0x40015800
#define DBGMCU_IDCODE_L4_G4 0xE0042000
#define DBGMCU_IDCODE_L5 0xE0044000
#define UID64_DEVNUM 0x1FFF7580
#define UID64_IDS 0x1FFF7584
#define UID64_IDS_STM32WL 0x0080E115
#define STM32_FLASH_BANK_BASE 0x08000000
#define STM32_FLASH_S_BANK_BASE 0x0C000000