flash/stm32l4x: add support of STM32WL5x dual core
according the RM0453, the second core have a different Flash CR and SR registers for flash operations (called C2CR and C2SR). so we need to a different flash_regs than older L4 devices. @see stm32wl_cpu2_flash_regs the C2CR register don't contain LOCK and OPTLOCK bits, and this explain the addition of new register index called STM32_FLASH_CR_WLK_INDEX to look-up the CR with lock, to be used in locking/unlocking the flash. note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1, to solve this read the UID64 (IEEE 64-bit unique device ID register) Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6050 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI
committed by
Oleksij Rempel
Oleksij Rempel
parent
64fbd60787
commit
6c1e1a212a
@@ -12,16 +12,47 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32wlx
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}
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set _ENDIAN little
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if { [info exists DUAL_CORE] } {
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set $_CHIPNAME.DUAL_CORE $DUAL_CORE
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unset DUAL_CORE
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} else {
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set $_CHIPNAME.DUAL_CORE 0
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}
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if { [info exists WKUP_CM0P] } {
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set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
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unset WKUP_CM0P
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} else {
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set $_CHIPNAME.WKUP_CM0P 0
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}
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# Issue a warning when hla is used, and fallback to single core configuration
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if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
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echo "Warning : hla does not support multicore debugging"
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set $_CHIPNAME.DUAL_CORE 0
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set $_CHIPNAME.WKUP_CM0P 0
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}
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# setup the Work-area start address and size
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# Work-area is a space in RAM used for flash programming
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# By default use 20kB
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# Memory map for known devices:
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# STM32WL x5JC x5JB x5J8
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# FLASH 256 128 64
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# SRAM1 32 16 0
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# SRAM2 32 32 20
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# By default use 8kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x5000
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set _WORKAREASIZE 0x2000
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}
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# Use SRAM2 as work area (some devices do not have SRAM1):
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set WORKAREASTART_CM4 0x20008000
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set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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@@ -41,13 +72,104 @@ if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
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flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
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# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
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# 2 WS compliant with VOS=Range1 and 24 MHz.
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mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
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mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_CHIPNAME.cpu0 configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 500
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}
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$_CHIPNAME.cpu0 configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE004203C 0x00001800 0
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set _CHIPNAME [stm32wlx_get_chipname]
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global $_CHIPNAME.WKUP_CM0P
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if {[set $_CHIPNAME.WKUP_CM0P]} {
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stm32wlx_wkup_cm0p
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}
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}
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$_CHIPNAME.cpu0 configure -event trace-config {
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# nothing to do
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
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$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
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flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
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}
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proc stm32wlx_wkup_cm0p {} {
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set _CHIPNAME [stm32wlx_get_chipname]
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# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
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# PWR_CR4 |= C2BOOT
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stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
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}
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}
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# get _CHIPNAME from current target
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proc stm32wlx_get_chipname {} {
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set t [target current]
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set sep [string last "." $t]
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if {$sep == -1} {
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return $t
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}
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return [string range $t 0 [expr $sep - 1]]
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}
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# like mrw, but with target selection
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proc stm32wlx_mrw {used_target reg} {
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set value ""
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$used_target mem2array value 32 $reg 1
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return $value(0)
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}
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# like mmw, but with target selection
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proc stm32wlx_mmw {used_target reg setbits clearbits} {
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set old [stm32wlx_mrw $used_target $reg]
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set new [expr {($old & ~$clearbits) | $setbits}]
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$used_target mww $reg $new
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}
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# Make sure that cpu0 is selected
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targets $_CHIPNAME.cpu0
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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@@ -63,38 +185,3 @@ if {[using_jtag]} {
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
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# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
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# 2 WS compliant with VOS=Range1 and 24 MHz.
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mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
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mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 500
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE004203C 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# nothing to do
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}
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