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target: create/use register_cache_invalidate()

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Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:

 - armv4_5_invalidate_core_regs()
 - armv7m_invalidate_core_regs
 - mips32_invalidate_core_regs() too.

Make cache->num_regs be unsigned, avoiding various errors.

Net code shrink and simplification.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-11-19 19:02:10 -08:00
parent 31fb7788a6
commit 71cde5e359
14 changed files with 47 additions and 77 deletions
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11
src/target/arm7_9_common.c
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@@ -1040,7 +1040,7 @@ int arm7_9_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
{
@@ -1224,10 +1224,7 @@ int arm7_9_soft_reset_halt(struct target *target)
}
/* all register content is now invalid */
if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
{
return retval;
}
register_cache_invalidate(armv4_5->core_cache);
/* SVC, ARM state, IRQ and FIQ disabled */
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
@@ -1921,7 +1918,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
if (!debug_execution)
{
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
{
@@ -2064,7 +2061,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
arm7_9->disable_single_step(target);
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
register_cache_invalidate(armv4_5->core_cache);
if (err != ERROR_OK)
{