target: create/use register_cache_invalidate()
Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
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}
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swjdp_transaction_endcheck(swjdp);
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armv7m_invalidate_core_regs(target);
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register_cache_invalidate(cortex_m3->armv7m.core_cache);
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/* make sure we have latest dhcsr flags */
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mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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@@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
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target->state = TARGET_RESET;
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/* registers are now invalid */
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armv7m_invalidate_core_regs(target);
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register_cache_invalidate(cortex_m3->armv7m.core_cache);
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while (timeout < 100)
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{
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@@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
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target->debug_reason = DBG_REASON_NOTHALTED;
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/* registers are now invalid */
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armv7m_invalidate_core_regs(target);
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register_cache_invalidate(armv7m->core_cache);
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if (!debug_execution)
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{
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target->state = TARGET_RUNNING;
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@@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
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mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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/* registers are now invalid */
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armv7m_invalidate_core_regs(target);
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register_cache_invalidate(cortex_m3->armv7m.core_cache);
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if (breakpoint)
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cortex_m3_set_breakpoint(target, breakpoint);
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@@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
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target->state = TARGET_RESET;
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jtag_add_sleep(50000);
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armv7m_invalidate_core_regs(target);
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register_cache_invalidate(cortex_m3->armv7m.core_cache);
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if (target->reset_halt)
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{
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