target: create/use register_cache_invalidate()

Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:

 - armv4_5_invalidate_core_regs()
 - armv7m_invalidate_core_regs
 - mips32_invalidate_core_regs() too.

Make cache->num_regs be unsigned, avoiding various errors.

Net code shrink and simplification.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-11-19 19:02:10 -08:00
parent 31fb7788a6
commit 71cde5e359
14 changed files with 47 additions and 77 deletions

View File

@@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target)
}
swjdp_transaction_endcheck(swjdp);
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -510,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
target->state = TARGET_RESET;
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
while (timeout < 100)
{
@@ -617,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current,
target->debug_reason = DBG_REASON_NOTHALTED;
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(armv7m->core_cache);
if (!debug_execution)
{
target->state = TARGET_RUNNING;
@@ -673,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current,
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
@@ -812,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target)
target->state = TARGET_RESET;
jtag_add_sleep(50000);
armv7m_invalidate_core_regs(target);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
if (target->reset_halt)
{