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MIPS: remove ejtag_srst variant

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The mips_m4k_assert_reset has now been restructured
so the variant ejtag_srst is not required anymore.
The ejtag software reset will be used if the target does not
have srst connected.

Remove ejtag_srst from docs.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This commit is contained in:
Spencer Oliver
2010-03-16 12:48:53 +00:00
parent 051e2c99ab
commit 79ca05b106
3 changed files with 17 additions and 25 deletions
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8
doc/openocd.texi
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@@ -3453,14 +3453,6 @@ be detected and the normal reset behaviour used.
@item @code{fa526} -- resembles arm920 (w/o Thumb)
@item @code{feroceon} -- resembles arm926
@item @code{mips_m4k} -- a MIPS core. This supports one variant:
@itemize @minus
@item @code{ejtag_srst} ... Use this when debugging targets that do not
provide a functional SRST line on the EJTAG connector. This causes
OpenOCD to instead use an EJTAG software reset command to reset the
processor.
You still need to enable @option{srst} on the @command{reset_config}
command to enable OpenOCD hardware reset functionality.
@end itemize
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
There are several variants defined: