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Merge branch 'master' into from_upstream

Browse Source 
Conflicts:
	src/flash/nor/at91sam4.c
	src/flash/nor/at91sam4l.c
	src/flash/nor/at91samd.c
	src/flash/nor/ath79.c
	src/flash/nor/atsame5.c
	src/flash/nor/cfi.c
	src/flash/nor/core.c
	src/flash/nor/fespi.c
	src/flash/nor/kinetis.c
	src/flash/nor/kinetis_ke.c
	src/flash/nor/lpc2000.c
	src/flash/nor/niietcm4.c
	src/flash/nor/nrf5.c
	src/flash/nor/numicro.c
	src/flash/nor/pic32mx.c
	src/flash/nor/stm32h7x.c
	src/flash/nor/stm32lx.c
	src/flash/nor/stmsmi.c
	src/flash/nor/tcl.c
	src/flash/nor/tms470.c
	src/flash/nor/virtual.c
	src/flash/nor/xmc4xxx.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/server/gdb_server.c
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
This commit is contained in:
Tim Newsome
2019-04-03 12:38:27 -07:00
parent c089e6ae9a 11a2bfc2bc
commit 79f9672615
120 changed files with 1233 additions and 936 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/flash/nor/aduc702x.c
+1 -1
View File
@@ -378,7 +378,7 @@ static int aduc702x_check_flash_completion(struct target *target, unsigned int t
return ERROR_OK;
}
struct flash_driver aduc702x_flash = {
const struct flash_driver aduc702x_flash = {
.name = "aduc702x",
.flash_bank_command = aduc702x_flash_bank_command,
.erase = aduc702x_erase,
src/flash/nor/aducm360.c
+1 -1
View File
@@ -554,7 +554,7 @@ static int aducm360_check_flash_completion(struct target *target, unsigned int t
}
/* ----------------------------------------------------------------------- */
struct flash_driver aducm360_flash = {
const struct flash_driver aducm360_flash = {
.name = "aducm360",
.flash_bank_command = aducm360_flash_bank_command,
.erase = aducm360_erase,
src/flash/nor/ambiqmicro.c
+1 -1
View File
@@ -888,7 +888,7 @@ static const struct command_registration ambiqmicro_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver ambiqmicro_flash = {
const struct flash_driver ambiqmicro_flash = {
.name = "ambiqmicro",
.commands = ambiqmicro_command_handlers,
.flash_bank_command = ambiqmicro_flash_bank_command,
src/flash/nor/at91sam3.c
+2 -2
View File
@@ -109,7 +109,7 @@
#define offset_EFC_FSR 8
#define offset_EFC_FRR 12
extern struct flash_driver at91sam3_flash;
extern const struct flash_driver at91sam3_flash;
static float _tomhz(uint32_t freq_hz)
{
@@ -3753,7 +3753,7 @@ static const struct command_registration at91sam3_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam3_flash = {
const struct flash_driver at91sam3_flash = {
.name = "at91sam3",
.commands = at91sam3_command_handlers,
.flash_bank_command = sam3_flash_bank_command,
src/flash/nor/at91sam4.c
+5 -5
View File
@@ -103,7 +103,7 @@
#define offset_EFC_FSR 8
#define offset_EFC_FRR 12
extern struct flash_driver at91sam4_flash;
extern const struct flash_driver at91sam4_flash;
static float _tomhz(uint32_t freq_hz)
{
@@ -2598,7 +2598,7 @@ static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
}
snprintf(buf, buf_size,
"%s bank %d: %d kB at 0x%08" TARGET_PRIxADDR,
"%s bank %d: %d kB at " TARGET_ADDR_FMT,
pPrivate->pChip->details.name,
pPrivate->bank_number,
k,
@@ -2642,8 +2642,8 @@ static int sam4_probe(struct flash_bank *bank)
for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
bank->size = pPrivate->pChip->details.bank[x].size_bytes;
LOG_DEBUG("SAM4 Set flash bank to %" TARGET_PRIxADDR " - %"
TARGET_PRIxADDR ", idx %d", bank->base,
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
TARGET_ADDR_FMT ", idx %d", bank->base,
bank->base + bank->size, x);
break;
}
@@ -3234,7 +3234,7 @@ static const struct command_registration at91sam4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam4_flash = {
const struct flash_driver at91sam4_flash = {
.name = "at91sam4",
.commands = at91sam4_command_handlers,
.flash_bank_command = sam4_flash_bank_command,
src/flash/nor/at91sam4l.c
+2 -2
View File
@@ -203,7 +203,7 @@ static int sam4l_flash_command(struct target *target, uint8_t cmd, int page)
FLASH_BANK_COMMAND_HANDLER(sam4l_flash_bank_command)
{
if (bank->base != SAM4L_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR
LOG_ERROR("Address " TARGET_ADDR_FMT
" invalid bank address (try 0x%08" PRIx32
"[at91sam4l series] )",
bank->base, SAM4L_FLASH);
@@ -684,7 +684,7 @@ static const struct command_registration at91sam4l_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam4l_flash = {
const struct flash_driver at91sam4l_flash = {
.name = "at91sam4l",
.commands = at91sam4l_command_handlers,
.flash_bank_command = sam4l_flash_bank_command,
src/flash/nor/at91sam7.c
+1 -1
View File
@@ -1140,7 +1140,7 @@ static const struct command_registration at91sam7_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam7_flash = {
const struct flash_driver at91sam7_flash = {
.name = "at91sam7",
.usage = "gpnvm <bit> <set | clear>",
.commands = at91sam7_command_handlers,
src/flash/nor/at91samd.c
+2 -2
View File
@@ -906,7 +906,7 @@ free_pb:
FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR
LOG_ERROR("Address " TARGET_ADDR_FMT
" invalid bank address (try 0x%08" PRIx32
"[at91samd series] )",
bank->base, SAMD_FLASH);
@@ -1287,7 +1287,7 @@ static const struct command_registration at91samd_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91samd_flash = {
const struct flash_driver at91samd_flash = {
.name = "at91samd",
.commands = at91samd_command_handlers,
.flash_bank_command = samd_flash_bank_command,
src/flash/nor/ath79.c
+2 -2
View File
@@ -794,7 +794,7 @@ static int ath79_probe(struct flash_bank *bank)
ath79_info->io_base = target_device->io_base;
LOG_DEBUG("Found device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
retval = read_flash_id(bank, &id);
@@ -895,7 +895,7 @@ static int get_ath79_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver ath79_flash = {
const struct flash_driver ath79_flash = {
.name = "ath79",
.flash_bank_command = ath79_flash_bank_command,
.erase = ath79_erase,
src/flash/nor/atsame5.c
+2 -2
View File
@@ -730,7 +730,7 @@ free_pb:
FLASH_BANK_COMMAND_HANDLER(same5_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR " invalid bank address (try "
LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
"0x%08" PRIx32 "[same5] )", bank->base, SAMD_FLASH);
return ERROR_FAIL;
}
@@ -938,7 +938,7 @@ static const struct command_registration same5_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver atsame5_flash = {
const struct flash_driver atsame5_flash = {
.name = "atsame5",
.commands = same5_command_handlers,
.flash_bank_command = same5_flash_bank_command,
src/flash/nor/atsamv.c
+2 -2
View File
@@ -94,7 +94,7 @@
#define SAMV_PAGE_SIZE 512
#define SAMV_FLASH_BASE 0x00400000
extern struct flash_driver atsamv_flash;
extern const struct flash_driver atsamv_flash;
struct samv_flash_bank {
int probed;
@@ -726,7 +726,7 @@ static const struct command_registration atsamv_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver atsamv_flash = {
const struct flash_driver atsamv_flash = {
.name = "atsamv",
.commands = atsamv_command_handlers,
.flash_bank_command = samv_flash_bank_command,
src/flash/nor/avrf.c
+1 -1
View File
@@ -462,7 +462,7 @@ static const struct command_registration avrf_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver avr_flash = {
const struct flash_driver avr_flash = {
.name = "avr",
.commands = avrf_command_handlers,
.flash_bank_command = avrf_flash_bank_command,
src/flash/nor/bluenrg-x.c
+4 -4
View File
@@ -404,9 +404,9 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
/* Stack pointer for program working area */
buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
LOG_DEBUG("source->address = %08" TARGET_PRIxADDR, source->address);
LOG_DEBUG("source->address+ source->size = %08" TARGET_PRIxADDR, source->address+source->size);
LOG_DEBUG("write_algorithm_sp->address = %08" TARGET_PRIxADDR, write_algorithm_sp->address);
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
LOG_DEBUG("address = %08x", address+pre_size);
LOG_DEBUG("count = %08x", count);
@@ -539,7 +539,7 @@ static int bluenrgx_get_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver bluenrgx_flash = {
const struct flash_driver bluenrgx_flash = {
.name = "bluenrg-x",
.flash_bank_command = bluenrgx_flash_bank_command,
.erase = bluenrgx_erase,
src/flash/nor/cc26xx.c
+1 -1
View File
@@ -535,7 +535,7 @@ static int cc26xx_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver cc26xx_flash = {
const struct flash_driver cc26xx_flash = {
.name = "cc26xx",
.flash_bank_command = cc26xx_flash_bank_command,
.erase = cc26xx_erase,
src/flash/nor/cc3220sf.c
+1 -1
View File
@@ -489,7 +489,7 @@ static int cc3220sf_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver cc3220sf_flash = {
const struct flash_driver cc3220sf_flash = {
.name = "cc3220sf",
.flash_bank_command = cc3220sf_flash_bank_command,
.erase = cc3220sf_erase,
src/flash/nor/cfi.c
+12 -12
View File
@@ -889,8 +889,8 @@ static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
TARGET_PRIxADDR, i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -937,8 +937,8 @@ static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
TARGET_PRIxADDR, i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -2001,7 +2001,7 @@ static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write word at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
", address 0x%" PRIx32,
bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2027,7 +2027,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
/* Check for valid range */
if (address & buffermask) {
LOG_ERROR("Write address at base 0x%" TARGET_PRIxADDR ", address 0x%"
LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%"
PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2057,7 +2057,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
return retval;
LOG_ERROR(
"couldn't start buffer write operation at base 0x%" TARGET_PRIxADDR
"couldn't start buffer write operation at base " TARGET_ADDR_FMT
", address 0x%" PRIx32,
bank->base,
address);
@@ -2087,7 +2087,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
if (retval != ERROR_OK)
return retval;
LOG_ERROR("Buffer write at base 0x%" TARGET_PRIxADDR
LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2123,7 +2123,7 @@ static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint3
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write word at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
", address 0x%" PRIx32, bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2149,7 +2149,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word
/* Check for valid range */
if (address & buffermask) {
LOG_ERROR("Write address at base 0x%" TARGET_PRIxADDR
LOG_ERROR("Write address at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2195,7 +2195,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write block at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
@@ -3112,7 +3112,7 @@ static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *par
cfi_info->buf_write_timeout_typ = 0;
}
struct flash_driver cfi_flash = {
const struct flash_driver cfi_flash = {
.name = "cfi",
.flash_bank_command = cfi_flash_bank_command,
.erase = cfi_erase,
src/flash/nor/core.c
+29 -30
View File
@@ -99,7 +99,7 @@ int flash_driver_write(struct flash_bank *bank,
retval = bank->driver->write(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
"error writing to flash at address 0x%08" TARGET_PRIxADDR
"error writing to flash at address " TARGET_ADDR_FMT
" at offset 0x%8.8" PRIx32,
bank->base,
offset);
@@ -118,7 +118,7 @@ int flash_driver_read(struct flash_bank *bank,
retval = bank->driver->read(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
"error reading to flash at address 0x%08" TARGET_PRIxADDR
"error reading to flash at address " TARGET_ADDR_FMT
" at offset 0x%8.8" PRIx32,
bank->base,
offset);
@@ -270,7 +270,7 @@ int get_flash_bank_by_num(int num, struct flash_bank **bank)
/* lookup flash bank by address, bank not found is success, but
* result_bank is set to NULL. */
int get_flash_bank_by_addr(struct target *target,
uint32_t addr,
target_addr_t addr,
bool check,
struct flash_bank **result_bank)
{
@@ -296,7 +296,7 @@ int get_flash_bank_by_addr(struct target *target,
}
*result_bank = NULL;
if (check) {
LOG_ERROR("No flash at address 0x%08" PRIx32, addr);
LOG_ERROR("No flash at address " TARGET_ADDR_FMT, addr);
return ERROR_FAIL;
}
return ERROR_OK;
@@ -416,13 +416,13 @@ int default_flash_blank_check(struct flash_bank *bank)
* warning about those additions.
*/
static int flash_iterate_address_range_inner(struct target *target,
char *pad_reason, uint32_t addr, uint32_t length,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
struct flash_bank *c;
struct flash_sector *block_array;
uint32_t last_addr = addr + length; /* first address AFTER end */
target_addr_t last_addr = addr + length - 1; /* the last address of range */
int first = -1;
int last = -1;
int i;
@@ -448,7 +448,7 @@ static int flash_iterate_address_range_inner(struct target *target,
}
/* check whether it all fits in this bank */
if (addr + length - 1 > c->base + c->size - 1) {
if (last_addr > c->base + c->size - 1) {
LOG_ERROR("Flash access does not fit into bank.");
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -466,21 +466,19 @@ static int flash_iterate_address_range_inner(struct target *target,
num_blocks = c->num_sectors;
}
addr -= c->base;
last_addr -= c->base;
for (i = 0; i < num_blocks; i++) {
struct flash_sector *f = &block_array[i];
uint32_t end = f->offset + f->size;
target_addr_t sector_addr = c->base + f->offset;
target_addr_t sector_last_addr = sector_addr + f->size - 1;
/* start only on a sector boundary */
if (first < 0) {
/* scanned past the first sector? */
if (addr < f->offset)
if (addr < sector_addr)
break;
/* is this the first sector? */
if (addr == f->offset)
if (addr == sector_addr)
first = i;
/* Does this need head-padding? If so, pad and warn;
@@ -490,20 +488,20 @@ static int flash_iterate_address_range_inner(struct target *target,
* ever know if that data was in use. The warning
* should help users sort out messes later.
*/
else if (addr < end && pad_reason) {
else if (addr <= sector_last_addr && pad_reason) {
/* FIXME say how many bytes (e.g. 80 KB) */
LOG_WARNING("Adding extra %s range, "
"%#8.8x to %#8.8x",
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
pad_reason,
(unsigned) f->offset,
(unsigned) addr - 1);
sector_addr,
addr - 1);
first = i;
} else
continue;
}
/* is this (also?) the last sector? */
if (last_addr == end) {
if (last_addr == sector_last_addr) {
last = i;
break;
}
@@ -511,28 +509,28 @@ static int flash_iterate_address_range_inner(struct target *target,
/* Does this need tail-padding? If so, pad and warn;
* or else force an error.
*/
if (last_addr < end && pad_reason) {
if (last_addr < sector_last_addr && pad_reason) {
/* FIXME say how many bytes (e.g. 80 KB) */
LOG_WARNING("Adding extra %s range, "
"%#8.8x to %#8.8x",
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
pad_reason,
(unsigned) last_addr,
(unsigned) end - 1);
last_addr + 1,
sector_last_addr);
last = i;
break;
}
/* MUST finish on a sector boundary */
if (last_addr <= f->offset)
if (last_addr < sector_addr)
break;
}
/* invalid start or end address? */
if (first == -1 || last == -1) {
LOG_ERROR("address range 0x%8.8x .. 0x%8.8x "
"is not sector-aligned",
(unsigned) (c->base + addr),
(unsigned) (c->base + last_addr - 1));
LOG_ERROR("address range " TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT
" is not sector-aligned",
addr,
last_addr);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -547,7 +545,7 @@ static int flash_iterate_address_range_inner(struct target *target,
* multiple chips.
*/
static int flash_iterate_address_range(struct target *target,
char *pad_reason, uint32_t addr, uint32_t length,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
@@ -581,7 +579,7 @@ static int flash_iterate_address_range(struct target *target,
}
int flash_erase_address_range(struct target *target,
bool pad, uint32_t addr, uint32_t length)
bool pad, target_addr_t addr, uint32_t length)
{
return flash_iterate_address_range(target, pad ? "erase" : NULL,
addr, length, false, &flash_driver_erase);
@@ -592,7 +590,8 @@ static int flash_driver_unprotect(struct flash_bank *bank, int first, int last)
return flash_driver_protect(bank, 0, first, last);
}
int flash_unlock_address_range(struct target *target, uint32_t addr, uint32_t length)
int flash_unlock_address_range(struct target *target, target_addr_t addr,
uint32_t length)
{
/* By default, pad to sector boundaries ... the real issue here
* is that our (only) caller *permanently* removes protection,
src/flash/nor/core.h
+4 -4
View File
@@ -87,7 +87,7 @@ struct flash_bank {
struct target *target; /**< Target to which this bank belongs. */
struct flash_driver *driver; /**< Driver for this bank. */
const struct flash_driver *driver; /**< Driver for this bank. */
void *driver_priv; /**< Private driver storage pointer */
int bank_number; /**< The 'bank' (or chip number) of this instance. */
@@ -149,9 +149,9 @@ int flash_register_commands(struct command_context *cmd_ctx);
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int flash_erase_address_range(struct target *target,
bool pad, uint32_t addr, uint32_t length);
bool pad, target_addr_t addr, uint32_t length);
int flash_unlock_address_range(struct target *target, uint32_t addr,
int flash_unlock_address_range(struct target *target, target_addr_t addr,
uint32_t length);
/**
@@ -263,7 +263,7 @@ struct flash_bank *get_flash_bank_by_num_noprobe(int num);
* @param check return ERROR_OK and result_bank NULL if the bank does not exist
* @returns The struct flash_bank located at @a addr, or NULL.
*/
int get_flash_bank_by_addr(struct target *target, uint32_t addr, bool check,
int get_flash_bank_by_addr(struct target *target, target_addr_t addr, bool check,
struct flash_bank **result_bank);
/**
* Allocate and fill an array of sectors or protection blocks.
src/flash/nor/driver.h
+1 -1
View File
@@ -231,6 +231,6 @@ struct flash_driver {
* @param name The name of the requested driver.
* @returns The flash_driver called @c name, or NULL if not found.
*/
struct flash_driver *flash_driver_find_by_name(const char *name);
const struct flash_driver *flash_driver_find_by_name(const char *name);
#endif /* OPENOCD_FLASH_NOR_DRIVER_H */
src/flash/nor/drivers.c
+65 -65
View File
@@ -20,75 +20,75 @@
#endif
#include "imp.h"
extern struct flash_driver aduc702x_flash;
extern struct flash_driver aducm360_flash;
extern struct flash_driver ambiqmicro_flash;
extern struct flash_driver at91sam3_flash;
extern struct flash_driver at91sam4_flash;
extern struct flash_driver at91sam4l_flash;
extern struct flash_driver at91sam7_flash;
extern struct flash_driver at91samd_flash;
extern struct flash_driver ath79_flash;
extern struct flash_driver atsame5_flash;
extern struct flash_driver atsamv_flash;
extern struct flash_driver avr_flash;
extern struct flash_driver bluenrgx_flash;
extern struct flash_driver cc3220sf_flash;
extern struct flash_driver cc26xx_flash;
extern struct flash_driver cfi_flash;
extern struct flash_driver dsp5680xx_flash;
extern struct flash_driver efm32_flash;
extern struct flash_driver em357_flash;
extern struct flash_driver esirisc_flash;
extern struct flash_driver faux_flash;
extern struct flash_driver fm3_flash;
extern struct flash_driver fm4_flash;
extern struct flash_driver fespi_flash;
extern struct flash_driver jtagspi_flash;
extern struct flash_driver kinetis_flash;
extern struct flash_driver kinetis_ke_flash;
extern struct flash_driver lpc2000_flash;
extern struct flash_driver lpc288x_flash;
extern struct flash_driver lpc2900_flash;
extern struct flash_driver lpcspifi_flash;
extern struct flash_driver max32xxx_flash;
extern struct flash_driver mdr_flash;
extern struct flash_driver mrvlqspi_flash;
extern struct flash_driver msp432_flash;
extern struct flash_driver niietcm4_flash;
extern struct flash_driver nrf5_flash;
extern struct flash_driver nrf51_flash;
extern struct flash_driver numicro_flash;
extern struct flash_driver ocl_flash;
extern struct flash_driver pic32mx_flash;
extern struct flash_driver psoc4_flash;
extern struct flash_driver psoc5lp_flash;
extern struct flash_driver psoc5lp_eeprom_flash;
extern struct flash_driver psoc5lp_nvl_flash;
extern struct flash_driver psoc6_flash;
extern struct flash_driver sim3x_flash;
extern struct flash_driver stellaris_flash;
extern struct flash_driver stm32f1x_flash;
extern struct flash_driver stm32f2x_flash;
extern struct flash_driver stm32lx_flash;
extern struct flash_driver stm32l4x_flash;
extern struct flash_driver stm32h7x_flash;
extern struct flash_driver stmsmi_flash;
extern struct flash_driver str7x_flash;
extern struct flash_driver str9x_flash;
extern struct flash_driver str9xpec_flash;
extern struct flash_driver tms470_flash;
extern struct flash_driver virtual_flash;
extern struct flash_driver w600_flash;
extern struct flash_driver xcf_flash;
extern struct flash_driver xmc1xxx_flash;
extern struct flash_driver xmc4xxx_flash;
extern const struct flash_driver aduc702x_flash;
extern const struct flash_driver aducm360_flash;
extern const struct flash_driver ambiqmicro_flash;
extern const struct flash_driver at91sam3_flash;
extern const struct flash_driver at91sam4_flash;
extern const struct flash_driver at91sam4l_flash;
extern const struct flash_driver at91sam7_flash;
extern const struct flash_driver at91samd_flash;
extern const struct flash_driver ath79_flash;
extern const struct flash_driver atsame5_flash;
extern const struct flash_driver atsamv_flash;
extern const struct flash_driver avr_flash;
extern const struct flash_driver bluenrgx_flash;
extern const struct flash_driver cc3220sf_flash;
extern const struct flash_driver cc26xx_flash;
extern const struct flash_driver cfi_flash;
extern const struct flash_driver dsp5680xx_flash;
extern const struct flash_driver efm32_flash;
extern const struct flash_driver em357_flash;
extern const struct flash_driver esirisc_flash;
extern const struct flash_driver faux_flash;
extern const struct flash_driver fm3_flash;
extern const struct flash_driver fm4_flash;
extern const struct flash_driver fespi_flash;
extern const struct flash_driver jtagspi_flash;
extern const struct flash_driver kinetis_flash;
extern const struct flash_driver kinetis_ke_flash;
extern const struct flash_driver lpc2000_flash;
extern const struct flash_driver lpc288x_flash;
extern const struct flash_driver lpc2900_flash;
extern const struct flash_driver lpcspifi_flash;
extern const struct flash_driver max32xxx_flash;
extern const struct flash_driver mdr_flash;
extern const struct flash_driver mrvlqspi_flash;
extern const struct flash_driver msp432_flash;
extern const struct flash_driver niietcm4_flash;
extern const struct flash_driver nrf5_flash;
extern const struct flash_driver nrf51_flash;
extern const struct flash_driver numicro_flash;
extern const struct flash_driver ocl_flash;
extern const struct flash_driver pic32mx_flash;
extern const struct flash_driver psoc4_flash;
extern const struct flash_driver psoc5lp_flash;
extern const struct flash_driver psoc5lp_eeprom_flash;
extern const struct flash_driver psoc5lp_nvl_flash;
extern const struct flash_driver psoc6_flash;
extern const struct flash_driver sim3x_flash;
extern const struct flash_driver stellaris_flash;
extern const struct flash_driver stm32f1x_flash;
extern const struct flash_driver stm32f2x_flash;
extern const struct flash_driver stm32lx_flash;
extern const struct flash_driver stm32l4x_flash;
extern const struct flash_driver stm32h7x_flash;
extern const struct flash_driver stmsmi_flash;
extern const struct flash_driver str7x_flash;
extern const struct flash_driver str9x_flash;
extern const struct flash_driver str9xpec_flash;
extern const struct flash_driver tms470_flash;
extern const struct flash_driver virtual_flash;
extern const struct flash_driver w600_flash;
extern const struct flash_driver xcf_flash;
extern const struct flash_driver xmc1xxx_flash;
extern const struct flash_driver xmc4xxx_flash;
/**
* The list of built-in flash drivers.
* @todo Make this dynamically extendable with loadable modules.
*/
static struct flash_driver *flash_drivers[] = {
static const struct flash_driver * const flash_drivers[] = {
&aduc702x_flash,
&aducm360_flash,
&ambiqmicro_flash,
@@ -155,7 +155,7 @@ static struct flash_driver *flash_drivers[] = {
NULL,
};
struct flash_driver *flash_driver_find_by_name(const char *name)
const struct flash_driver *flash_driver_find_by_name(const char *name)
{
for (unsigned i = 0; flash_drivers[i]; i++) {
if (strcmp(name, flash_drivers[i]->name) == 0)
src/flash/nor/dsp5680xx_flash.c
+1 -1
View File
@@ -256,7 +256,7 @@ static int dsp5680xx_flash_erase_check(struct flash_bank *bank)
return retval;
}
struct flash_driver dsp5680xx_flash = {
const struct flash_driver dsp5680xx_flash = {
.name = "dsp5680xx_flash",
.flash_bank_command = dsp5680xx_flash_bank_command,
.erase = dsp5680xx_flash_erase,
src/flash/nor/efm32.c
+1 -1
View File
@@ -1120,7 +1120,7 @@ static const struct command_registration efm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver efm32_flash = {
const struct flash_driver efm32_flash = {
.name = "efm32",
.commands = efm32x_command_handlers,
.flash_bank_command = efm32x_flash_bank_command,
src/flash/nor/em357.c
+1 -1
View File
@@ -929,7 +929,7 @@ static const struct command_registration em357_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver em357_flash = {
const struct flash_driver em357_flash = {
.name = "em357",
.commands = em357_command_handlers,
.flash_bank_command = em357_flash_bank_command,
src/flash/nor/esirisc_flash.c
+1 -1
View File
@@ -571,7 +571,7 @@ static const struct command_registration esirisc_flash_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver esirisc_flash = {
const struct flash_driver esirisc_flash = {
.name = "esirisc",
.usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
"cfg_address clock_hz wait_states",
src/flash/nor/faux.c
+1 -1
View File
@@ -113,7 +113,7 @@ static const struct command_registration faux_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver faux_flash = {
const struct flash_driver faux_flash = {
.name = "faux",
.commands = faux_command_handlers,
.flash_bank_command = faux_flash_bank_command,
src/flash/nor/fespi.c
+10 -10
View File
@@ -160,7 +160,7 @@ FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
fespi_info->ctrl_base = 0;
if (CMD_ARGC >= 7) {
COMMAND_PARSE_ADDRESS(CMD_ARGV[6], fespi_info->ctrl_base);
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%" TARGET_PRIxADDR,
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi_info->ctrl_base);
}
@@ -174,7 +174,7 @@ static int fespi_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_
int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
LOG_ERROR("fespi_read_reg() error at 0x%" TARGET_PRIxADDR,
LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
fespi_info->ctrl_base + address);
return result;
}
@@ -188,7 +188,7 @@ static int fespi_write_reg(struct flash_bank *bank, target_addr_t address, uint3
int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
LOG_ERROR("fespi_write_reg() error writing 0x%x to 0x%" TARGET_PRIxADDR,
LOG_ERROR("fespi_write_reg() error writing 0x%x to " TARGET_ADDR_FMT,
value, fespi_info->ctrl_base + address);
return result;
}
@@ -707,7 +707,7 @@ static int steps_execute(struct algorithm_steps *as,
data_buf);
free(data_buf);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to write data to 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
data_wa->address, retval);
goto exit;
}
@@ -716,7 +716,7 @@ static int steps_execute(struct algorithm_steps *as,
algorithm_wa->address, algorithm_wa->address + 4,
10000, NULL);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
goto exit;
}
@@ -773,7 +773,7 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
retval = target_write_buffer(target, algorithm_wa->address,
sizeof(algorithm_bin), algorithm_bin);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
target_free_working_area(target, algorithm_wa);
algorithm_wa = NULL;
@@ -933,12 +933,12 @@ static int fespi_probe(struct flash_bank *bank)
fespi_info->ctrl_base = target_device->ctrl_base;
LOG_DEBUG("Valid FESPI on device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
} else {
LOG_DEBUG("Assuming FESPI as specified at address 0x%" TARGET_PRIxADDR
" with ctrl at 0x%" TARGET_PRIxADDR, fespi_info->ctrl_base,
LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
" with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
bank->base);
}
@@ -1036,7 +1036,7 @@ static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver fespi_flash = {
const struct flash_driver fespi_flash = {
.name = "fespi",
.flash_bank_command = fespi_flash_bank_command,
.erase = fespi_erase,
src/flash/nor/fm3.c
+1 -1
View File
@@ -988,7 +988,7 @@ static const struct command_registration fm3_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver fm3_flash = {
const struct flash_driver fm3_flash = {
.name = "fm3",
.commands = fm3_command_handlers,
.flash_bank_command = fm3_flash_bank_command,
src/flash/nor/fm4.c
+2 -2
View File
@@ -272,7 +272,7 @@ static int fm4_flash_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t halfwords = MIN(halfword_count, data_workarea->size / 2);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(halfwords * 2, byte_count), data_workarea->address);
retval = target_write_buffer(target, data_workarea->address,
@@ -702,7 +702,7 @@ static const struct command_registration fm4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver fm4_flash = {
const struct flash_driver fm4_flash = {
.name = "fm4",
.commands = fm4_command_handlers,
.flash_bank_command = fm4_flash_bank_command,
src/flash/nor/jtagspi.c
+1 -1
View File
@@ -427,7 +427,7 @@ static int jtagspi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver jtagspi_flash = {
const struct flash_driver jtagspi_flash = {
.name = "jtagspi",
.flash_bank_command = jtagspi_flash_bank_command,
.erase = jtagspi_erase,
src/flash/nor/kinetis.c
+10 -10
View File
@@ -393,7 +393,7 @@ static bool fcf_fopt_configured;
static bool create_banks;
struct flash_driver kinetis_flash;
const struct flash_driver kinetis_flash;
static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count);
static int kinetis_probe_chip(struct kinetis_chip *k_chip);
@@ -1755,14 +1755,14 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer_aligned);
LOG_DEBUG("section @ %08" TARGET_PRIxADDR " aligned begin %" PRIu32
LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
", end %" PRIu32,
bank->base + offset, align_begin, align_end);
} else
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer);
LOG_DEBUG("write section @ %08" TARGET_PRIxADDR " with length %" PRIu32
LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
" bytes",
bank->base + offset, size);
@@ -1778,13 +1778,13 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
LOG_ERROR("Error writing section at %08" TARGET_PRIxADDR,
LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
bank->base + offset);
break;
}
if (ftfx_fstat & 0x01) {
LOG_ERROR("Flash write error at %08" TARGET_PRIxADDR,
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
bank->base + offset);
if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
&& (k_chip->flash_support & FS_WIDTH_256BIT)) {
@@ -1824,7 +1824,7 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
}
}
LOG_DEBUG("flash write @ %08" TARGET_PRIxADDR, bank->base + offset);
LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
if (fallback == 0) {
/* program section command */
@@ -1877,13 +1877,13 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
LOG_ERROR("Error writing longword at %08" TARGET_PRIxADDR,
LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
bank->base + offset);
break;
}
if (ftfx_fstat & 0x01)
LOG_ERROR("Flash write error at %08" TARGET_PRIxADDR,
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
bank->base + offset);
buffer += 4;
@@ -2775,7 +2775,7 @@ static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
uint32_t size_k = bank->size / 1024;
snprintf(buf, buf_size,
"%s %s: %" PRIu32 "k %s bank %s at 0x%08" TARGET_PRIxADDR,
"%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
bank->driver->name, k_chip->name,
size_k, bank_class_names[k_bank->flash_class],
bank->name, bank->base);
@@ -3143,7 +3143,7 @@ static const struct command_registration kinetis_command_handler[] = {
struct flash_driver kinetis_flash = {
const struct flash_driver kinetis_flash = {
.name = "kinetis",
.commands = kinetis_command_handler,
.flash_bank_command = kinetis_flash_bank_command,
src/flash/nor/kinetis_ke.c
+2 -2
View File
@@ -1175,7 +1175,7 @@ static int kinetis_ke_auto_probe(struct flash_bank *bank)
static int kinetis_ke_info(struct flash_bank *bank, char *buf, int buf_size)
{
(void) snprintf(buf, buf_size,
"%s driver for flash bank %s at 0x%8.8" TARGET_PRIxADDR,
"%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, bank->name, bank->base);
return ERROR_OK;
@@ -1297,7 +1297,7 @@ static const struct command_registration kinetis_ke_command_handler[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver kinetis_ke_flash = {
const struct flash_driver kinetis_ke_flash = {
.name = "kinetis_ke",
.commands = kinetis_ke_command_handler,
.flash_bank_command = kinetis_ke_flash_bank_command,
src/flash/nor/lpc2000.c
+3 -3
View File
@@ -719,7 +719,7 @@ static int lpc2000_iap_working_area_init(struct flash_bank *bank, struct working
int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate);
if (retval != ERROR_OK) {
LOG_ERROR("Write memory at address 0x%8.8" TARGET_PRIxADDR " failed (check work_area definition)",
LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
(*iap_working_area)->address);
target_free_working_area(target, *iap_working_area);
}
@@ -1186,7 +1186,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
free(last_buffer);
}
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
@@ -1609,7 +1609,7 @@ static const struct command_registration lpc2000_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver lpc2000_flash = {
const struct flash_driver lpc2000_flash = {
.name = "lpc2000",
.commands = lpc2000_command_handlers,
.flash_bank_command = lpc2000_flash_bank_command,
src/flash/nor/lpc288x.c
+1 -1
View File
@@ -412,7 +412,7 @@ static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last
return ERROR_OK;
}
struct flash_driver lpc288x_flash = {
const struct flash_driver lpc288x_flash = {
.name = "lpc288x",
.flash_bank_command = lpc288x_flash_bank_command,
.erase = lpc288x_erase,
src/flash/nor/lpc2900.c
+1 -1
View File
@@ -1581,7 +1581,7 @@ static int lpc2900_protect_check(struct flash_bank *bank)
return lpc2900_read_security_status(bank);
}
struct flash_driver lpc2900_flash = {
const struct flash_driver lpc2900_flash = {
.name = "lpc2900",
.commands = lpc2900_command_handlers,
.flash_bank_command = lpc2900_flash_bank_command,
src/flash/nor/lpcspifi.c
+2 -2
View File
@@ -186,7 +186,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
return retval;
}
LOG_DEBUG("Writing algorithm to working area at 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
spifi_init_algorithm->address);
/* Write algorithm to working area */
retval = target_write_buffer(target,
@@ -946,7 +946,7 @@ static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver lpcspifi_flash = {
const struct flash_driver lpcspifi_flash = {
.name = "lpcspifi",
.flash_bank_command = lpcspifi_flash_bank_command,
.erase = lpcspifi_erase,
src/flash/nor/max32xxx.c
+1 -1
View File
@@ -981,7 +981,7 @@ static const struct command_registration max32xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver max32xxx_flash = {
const struct flash_driver max32xxx_flash = {
.name = "max32xxx",
.commands = max32xxx_command_handlers,
.flash_bank_command = max32xxx_flash_bank_command,
src/flash/nor/mdr.c
+1 -1
View File
@@ -609,7 +609,7 @@ static int get_mdr_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver mdr_flash = {
const struct flash_driver mdr_flash = {
.name = "mdr",
.usage = "flash bank <name> mdr <base> <size> 0 0 <target#> <type> <page_count> <sec_count>\n"
"<type>: 0 for main memory, 1 for info memory",
src/flash/nor/mrvlqspi.c
+1 -1
View File
@@ -953,7 +953,7 @@ FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
return ERROR_OK;
}
struct flash_driver mrvlqspi_flash = {
const struct flash_driver mrvlqspi_flash = {
.name = "mrvlqspi",
.flash_bank_command = mrvlqspi_flash_bank_command,
.erase = mrvlqspi_flash_erase,
src/flash/nor/msp432.c
+1 -1
View File
@@ -1075,7 +1075,7 @@ static const struct command_registration msp432_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver msp432_flash = {
const struct flash_driver msp432_flash = {
.name = "msp432",
.commands = msp432_command_handlers,
.flash_bank_command = msp432_flash_bank_command,
src/flash/nor/niietcm4.c
+2 -2
View File
@@ -1585,7 +1585,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
char info_bootflash_addr_str[64];
if (niietcm4_info->bflash_info_remap)
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
"0x%" TARGET_PRIxADDR " base adress", bank->base);
TARGET_ADDR_FMT " base adress", bank->base);
else
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
"not mapped to global adress space");
@@ -1729,7 +1729,7 @@ static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size)
}
struct flash_driver niietcm4_flash = {
const struct flash_driver niietcm4_flash = {
.name = "niietcm4",
.usage = "flash bank <name> niietcm4 <base> <size> 0 0 <target#>",
.commands = niietcm4_command_handlers,
src/flash/nor/nrf5.c
+3 -3
View File
@@ -906,7 +906,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
bank->bank_number = 1;
break;
default:
LOG_ERROR("Invalid bank address 0x%08" TARGET_PRIxADDR, bank->base);
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
@@ -1140,7 +1140,7 @@ static const struct command_registration nrf5_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver nrf5_flash = {
const struct flash_driver nrf5_flash = {
.name = "nrf5",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,
@@ -1158,7 +1158,7 @@ struct flash_driver nrf5_flash = {
/* We need to retain the flash-driver name as well as the commands
* for backwards compatability */
struct flash_driver nrf51_flash = {
const struct flash_driver nrf51_flash = {
.name = "nrf51",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,
src/flash/nor/numicro.c
+3 -3
View File
@@ -1496,7 +1496,7 @@ static int numicro_erase(struct flash_bank *bank, int first, int last)
return retval;
for (i = first; i <= last; i++) {
LOG_DEBUG("erasing sector %d at address 0x%" TARGET_PRIxADDR, i,
LOG_DEBUG("erasing sector %d at address " TARGET_ADDR_FMT, i,
bank->base + bank->sectors[i].offset);
retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + bank->sectors[i].offset);
if (retval != ERROR_OK)
@@ -1679,7 +1679,7 @@ static int numicro_get_flash_size(struct flash_bank *bank, const struct numicro_
for (size_t i = 0; i < cpu->n_banks; i++) {
if (bank->base == cpu->bank[i].base) {
*flash_size = cpu->bank[i].size;
LOG_INFO("bank base = 0x%08" TARGET_PRIxADDR ", size = 0x%08"
LOG_INFO("bank base = " TARGET_ADDR_FMT ", size = 0x%08"
PRIx32, bank->base, *flash_size);
return ERROR_OK;
}
@@ -1871,7 +1871,7 @@ static const struct command_registration numicro_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver numicro_flash = {
const struct flash_driver numicro_flash = {
.name = "numicro",
.commands = numicro_command_handlers,
.flash_bank_command = numicro_flash_bank_command,
src/flash/nor/ocl.c
+1 -1
View File
@@ -314,7 +314,7 @@ static int ocl_auto_probe(struct flash_bank *bank)
return ERROR_OK;
}
struct flash_driver ocl_flash = {
const struct flash_driver ocl_flash = {
.name = "ocl",
.flash_bank_command = ocl_flash_bank_command,
.erase = ocl_erase,
src/flash/nor/pic32mx.c
+2 -2
View File
@@ -620,7 +620,7 @@ static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("writing to flash at address 0x%08" TARGET_PRIxADDR " at offset 0x%8.8" PRIx32
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
if (offset & 0x3) {
@@ -967,7 +967,7 @@ static const struct command_registration pic32mx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver pic32mx_flash = {
const struct flash_driver pic32mx_flash = {
.name = "pic32mx",
.commands = pic32mx_command_handlers,
.flash_bank_command = pic32mx_flash_bank_command,
src/flash/nor/psoc4.c
+1 -1
View File
@@ -950,7 +950,7 @@ static const struct command_registration psoc4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc4_flash = {
const struct flash_driver psoc4_flash = {
.name = "psoc4",
.commands = psoc4_command_handlers,
.flash_bank_command = psoc4_flash_bank_command,
src/flash/nor/psoc5lp.c
+4 -4
View File
@@ -838,7 +838,7 @@ static const struct command_registration psoc5lp_nvl_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_nvl_flash = {
const struct flash_driver psoc5lp_nvl_flash = {
.name = "psoc5lp_nvl",
.commands = psoc5lp_nvl_command_handlers,
.flash_bank_command = psoc5lp_nvl_flash_bank_command,
@@ -1036,7 +1036,7 @@ static const struct command_registration psoc5lp_eeprom_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_eeprom_flash = {
const struct flash_driver psoc5lp_eeprom_flash = {
.name = "psoc5lp_eeprom",
.commands = psoc5lp_eeprom_command_handlers,
.flash_bank_command = psoc5lp_eeprom_flash_bank_command,
@@ -1227,7 +1227,7 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer,
struct working_area *data_area = even_row ? even_row_area : odd_row_area;
unsigned len = MIN(ROW_SIZE, byte_count);
LOG_DEBUG("Writing load command for array %u row %u at 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
array_id, row, data_area->address);
psoc5lp_spc_write_opcode_buffer(target, buf, SPC_LOAD_ROW);
@@ -1548,7 +1548,7 @@ static const struct command_registration psoc5lp_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_flash = {
const struct flash_driver psoc5lp_flash = {
.name = "psoc5lp",
.commands = psoc5lp_command_handlers,
.flash_bank_command = psoc5lp_flash_bank_command,
src/flash/nor/psoc6.c
+1 -1
View File
@@ -1048,7 +1048,7 @@ static const struct command_registration psoc6_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc6_flash = {
const struct flash_driver psoc6_flash = {
.name = "psoc6",
.commands = psoc6_command_handlers,
.flash_bank_command = psoc6_flash_bank_command,
src/flash/nor/sim3x.c
+1 -1
View File
@@ -1110,7 +1110,7 @@ static const struct command_registration sim3x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver sim3x_flash = {
const struct flash_driver sim3x_flash = {
.name = "sim3x",
.commands = sim3x_command_handlers,
.flash_bank_command = sim3x_flash_bank_command,
src/flash/nor/stellaris.c
+1 -1
View File
@@ -1441,7 +1441,7 @@ static const struct command_registration stellaris_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stellaris_flash = {
const struct flash_driver stellaris_flash = {
.name = "stellaris",
.commands = stellaris_command_handlers,
.flash_bank_command = stellaris_flash_bank_command,
src/flash/nor/stm32f1x.c
+1 -1
View File
@@ -1570,7 +1570,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32f1x_flash = {
const struct flash_driver stm32f1x_flash = {
.name = "stm32f1x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32f2x.c
+212 -11
View File
@@ -123,6 +123,19 @@
/* Mass erase time can be as high as 32 s in x8 mode. */
#define FLASH_MASS_ERASE_TIMEOUT 33000
#define FLASH_BANK_BASE 0x80000000
#define STM32F2_OTP_SIZE 512
#define STM32F2_OTP_SECTOR_SIZE 32
#define STM32F2_OTP_BANK_BASE 0x1fff7800
#define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
/* see RM0410 section 3.6 "One-time programmable bytes" */
#define STM32F7_OTP_SECTOR_SIZE 64
#define STM32F7_OTP_SIZE 1024
#define STM32F7_OTP_BANK_BASE 0x1ff0f000
#define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
#define STM32_FLASH_BASE 0x40023c00
#define STM32_FLASH_ACR 0x40023c00
#define STM32_FLASH_KEYR 0x40023c04
@@ -185,7 +198,8 @@ struct stm32x_options {
struct stm32x_flash_bank {
struct stm32x_options option_bytes;
int probed;
bool probed;
bool otp_unlocked;
bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
bool has_extra_options; /* F42x/43x/469/479/7xx */
bool has_boot_addr; /* F7xx */
@@ -194,6 +208,49 @@ struct stm32x_flash_bank {
uint32_t user_bank_size;
};
static bool stm32x_is_otp(struct flash_bank *bank)
{
return bank->base == STM32F2_OTP_BANK_BASE ||
bank->base == STM32F7_OTP_BANK_BASE;
}
static bool stm32x_otp_is_f7(struct flash_bank *bank)
{
return bank->base == STM32F7_OTP_BANK_BASE;
}
static int stm32x_is_otp_unlocked(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
return stm32x_info->otp_unlocked;
}
static int stm32x_otp_disable(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
LOG_INFO("OTP memory bank #%d is disabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = false;
return ERROR_OK;
}
static int stm32x_otp_enable(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
if (!stm32x_info->otp_unlocked) {
LOG_INFO("OTP memory bank #%d is is enabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = true;
} else {
LOG_WARNING("OTP memory bank #%d is is already enabled for write commands.",
bank->bank_number);
}
return ERROR_OK;
}
/* flash bank stm32x <base> <size> 0 0 <target#>
*/
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
@@ -206,7 +263,8 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
bank->driver_priv = stm32x_info;
stm32x_info->probed = 0;
stm32x_info->probed = false;
stm32x_info->otp_unlocked = false;
stm32x_info->user_bank_size = bank->size;
return ERROR_OK;
@@ -460,14 +518,67 @@ static int stm32x_write_options(struct flash_bank *bank)
return ERROR_OK;
}
static int stm32x_otp_read_protect(struct flash_bank *bank)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
for (i = 0; i < bank->num_sectors; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
bank->sectors[i].is_protected = !lock;
}
return ERROR_OK;
}
static int stm32x_otp_protect(struct flash_bank *bank, int first, int last)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
for (i = first; first <= last; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
if (lock)
continue;
lock = 0xff;
retval = target_write_u8(target, lock_base + i, lock);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int stm32x_protect_check(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct flash_sector *prot_blocks;
int num_prot_blocks;
int retval;
/* if it's the OTP bank, look at the lock bits there */
if (stm32x_is_otp(bank))
return stm32x_otp_read_protect(bank);
/* read write protection settings */
int retval = stm32x_read_options(bank);
retval = stm32x_read_options(bank);
if (retval != ERROR_OK) {
LOG_DEBUG("unable to read option bytes");
return retval;
@@ -494,6 +605,11 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
struct target *target = bank->target;
int i;
if (stm32x_is_otp(bank)) {
LOG_ERROR("Cannot erase OTP memory");
return ERROR_FAIL;
}
assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
@@ -553,6 +669,13 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_TARGET_NOT_HALTED;
}
if (stm32x_is_otp(bank)) {
if (!set)
return ERROR_COMMAND_ARGUMENT_INVALID;
return stm32x_otp_protect(bank, first, last);
}
/* read protection settings */
int retval = stm32x_read_options(bank);
if (retval != ERROR_OK) {
@@ -590,6 +713,11 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
#include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
};
if (stm32x_is_otp(bank) && !stm32x_is_otp_unlocked(bank)) {
LOG_ERROR("OTP memory bank is disabled for write commands.");
return ERROR_FAIL;
}
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
@@ -774,7 +902,7 @@ static int setup_sector(struct flash_bank *bank, int start, int num, int size)
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
LOG_DEBUG("sector %d: %d kBytes", i, size >> 10);
}
return start + num;
@@ -828,15 +956,17 @@ static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i, num_prot_blocks;
int i, num_prot_blocks, num_sectors;
uint16_t flash_size_in_kb;
uint16_t otp_size_in_b;
uint16_t otp_sector_size;
uint32_t flash_size_reg = 0x1FFF7A22;
uint16_t max_sector_size_in_kb = 128;
uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t base_address = 0x08000000;
stm32x_info->probed = 0;
stm32x_info->probed = false;
stm32x_info->has_large_mem = false;
stm32x_info->has_boot_addr = false;
stm32x_info->has_extra_options = false;
@@ -856,6 +986,40 @@ static int stm32x_probe(struct flash_bank *bank)
bank->prot_blocks = NULL;
}
/* if explicitely called out as OTP bank, short circuit probe */
if (stm32x_is_otp(bank)) {
if (stm32x_otp_is_f7(bank)) {
otp_size_in_b = STM32F7_OTP_SIZE;
otp_sector_size = STM32F7_OTP_SECTOR_SIZE;
} else {
otp_size_in_b = STM32F2_OTP_SIZE;
otp_sector_size = STM32F2_OTP_SECTOR_SIZE;
}
num_sectors = otp_size_in_b / otp_sector_size;
LOG_INFO("flash size = %d bytes", otp_size_in_b);
assert(num_sectors > 0);
bank->num_sectors = num_sectors;
bank->sectors = calloc(sizeof(struct flash_sector), num_sectors);
if (stm32x_otp_is_f7(bank))
bank->size = STM32F7_OTP_SIZE;
else
bank->size = STM32F2_OTP_SIZE;
for (i = 0; i < num_sectors; i++) {
bank->sectors[i].offset = i * otp_sector_size;
bank->sectors[i].size = otp_sector_size;
bank->sectors[i].is_erased = 1;
bank->sectors[i].is_protected = 0;
}
stm32x_info->probed = true;
return ERROR_OK;
}
/* read stm32 device id register */
int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
@@ -945,7 +1109,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
LOG_INFO("flash size = %d kbytes", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
@@ -1040,7 +1204,7 @@ static int stm32x_probe(struct flash_bank *bank)
bank->num_prot_blocks = num_prot_blocks;
assert((bank->size >> 10) == flash_size_in_kb);
stm32x_info->probed = 1;
stm32x_info->probed = true;
return ERROR_OK;
}
@@ -1483,7 +1647,7 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
/* switching between single- and dual-bank modes requires re-probe */
/* ... and reprogramming of whole flash */
stm32x_info->probed = 0;
stm32x_info->probed = false;
command_print(CMD_CTX, "stm32f2x write options complete.\n"
"INFO: a reset or power cycle is required "
@@ -1533,6 +1697,37 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
return retval;
}
COMMAND_HANDLER(stm32x_handle_otp_command)
{
if (CMD_ARGC < 2) {
command_print(CMD_CTX, "stm32x otp <bank> (enable|disable|show)");
return ERROR_COMMAND_SYNTAX_ERROR;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
if (stm32x_is_otp(bank)) {
if (strcmp(CMD_ARGV[1], "enable") == 0) {
stm32x_otp_enable(bank);
} else if (strcmp(CMD_ARGV[1], "disable") == 0) {
stm32x_otp_disable(bank);
} else if (strcmp(CMD_ARGV[1], "show") == 0) {
command_print(CMD_CTX,
"OTP memory bank #%d is %s for write commands.",
bank->bank_number,
stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
} else {
return ERROR_COMMAND_SYNTAX_ERROR;
}
} else {
command_print(CMD_CTX, "Failed: not an OTP bank.");
}
return retval;
}
static const struct command_registration stm32x_exec_command_handlers[] = {
{
.name = "lock",
@@ -1576,7 +1771,13 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.usage = "bank_id optcr2",
.help = "Write optcr2 word",
},
{
.name = "otp",
.handler = stm32x_handle_otp_command,
.mode = COMMAND_EXEC,
.usage = "bank_id",
.help = "OTP (One Time Programmable) memory write enable/disable.",
},
COMMAND_REGISTRATION_DONE
};
@@ -1591,7 +1792,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32f2x_flash = {
const struct flash_driver stm32f2x_flash = {
.name = "stm32f2x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32h7x.c
+3 -17
View File
@@ -78,9 +78,6 @@
#define OPT_LOCK (1 << 0)
#define OPT_START (1 << 1)
/* FLASH_OPTCUR bit definitions (reading) */
#define IWDG1_HW (1 << 4)
/* register unlock keys */
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
@@ -109,7 +106,6 @@ struct stm32x_options {
uint8_t user_options;
uint8_t user2_options;
uint8_t user3_options;
uint8_t independent_watchdog_selection;
};
struct stm32h7x_part_info {
@@ -327,11 +323,6 @@ static int stm32x_read_options(struct flash_bank *bank)
stm32x_info->option_bytes.user2_options = (optiondata >> 16) & 0xff;
stm32x_info->option_bytes.user3_options = (optiondata >> 24) & 0x83;
if (optiondata & IWDG1_HW)
stm32x_info->option_bytes.independent_watchdog_selection = 1;
else
stm32x_info->option_bytes.independent_watchdog_selection = 0;
if (stm32x_info->option_bytes.RDP != 0xAA)
LOG_INFO("Device Security Bit Set");
@@ -368,11 +359,6 @@ static int stm32x_write_options(struct flash_bank *bank)
optiondata |= (stm32x_info->option_bytes.user2_options & 0xff) << 16;
optiondata |= (stm32x_info->option_bytes.user3_options & 0x83) << 24;
if (stm32x_info->option_bytes.independent_watchdog_selection)
optiondata |= IWDG1_HW;
else
optiondata &= ~IWDG1_HW;
/* program options */
retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTPRG, optiondata);
if (retval != ERROR_OK)
@@ -833,8 +819,8 @@ static int stm32x_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
} else {
LOG_WARNING("STM32H flash bank base address config is incorrect."
" 0x%" TARGET_PRIxADDR " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
LOG_WARNING("STM32H flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
@@ -1128,7 +1114,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32h7x_flash = {
const struct flash_driver stm32h7x_flash = {
.name = "stm32h7x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32l4x.c
+14 -3
View File
@@ -678,8 +678,9 @@ static int stm32l4_probe(struct flash_bank *bank)
/* Invalid FLASH size for this device. */
LOG_WARNING("Invalid flash size for STM32L4+ family device.");
return ERROR_FAIL;
default:
/* Other L4 family devices have 2K pages. */
case 0x461:
case 0x415:
/* These are dual-bank devices, we need to check the OPT_DBANK_LE_1M bit here */
page_size = 2048;
num_pages = flash_size_in_kb / 2;
/* check that calculation result makes sense */
@@ -689,6 +690,16 @@ static int stm32l4_probe(struct flash_bank *bank)
else
stm32l4_info->bank2_start = num_pages / 2;
break;
case 0x462:
case 0x435:
default:
/* These are single-bank devices */
page_size = 2048;
num_pages = flash_size_in_kb / 2;
/* check that calculation result makes sense */
assert(num_pages > 0);
stm32l4_info->bank2_start = UINT16_MAX;
break;
}
/* Release sector table if allocated. */
@@ -1042,7 +1053,7 @@ static const struct command_registration stm32l4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32l4x_flash = {
const struct flash_driver stm32l4x_flash = {
.name = "stm32l4x",
.commands = stm32l4_command_handlers,
.flash_bank_command = stm32l4_flash_bank_command,
src/flash/nor/stm32lx.c
+3 -3
View File
@@ -816,8 +816,8 @@ static int stm32lx_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
} else {
LOG_WARNING("STM32L flash bank base address config is incorrect."
" 0x%" TARGET_PRIxADDR " but should rather be 0x%" PRIx32
LOG_WARNING("STM32L flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
" or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
@@ -944,7 +944,7 @@ static const struct command_registration stm32lx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32lx_flash = {
const struct flash_driver stm32lx_flash = {
.name = "stm32lx",
.commands = stm32lx_command_handlers,
.flash_bank_command = stm32lx_flash_bank_command,
src/flash/nor/stmsmi.c
+3 -3
View File
@@ -559,13 +559,13 @@ static int stmsmi_probe(struct flash_bank *bank)
stmsmi_info->bank_num = SMI_SEL_BANK3;
break;
default:
LOG_ERROR("Invalid SMI base address 0x%" TARGET_PRIxADDR, bank->base);
LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
io_base = target_device->io_base;
stmsmi_info->io_base = io_base;
LOG_DEBUG("Valid SMI on device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
/* read and decode flash ID; returns in SW mode */
@@ -652,7 +652,7 @@ static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver stmsmi_flash = {
const struct flash_driver stmsmi_flash = {
.name = "stmsmi",
.flash_bank_command = stmsmi_flash_bank_command,
.erase = stmsmi_erase,
src/flash/nor/str7x.c
+1 -1
View File
@@ -799,7 +799,7 @@ static const struct command_registration str7x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str7x_flash = {
const struct flash_driver str7x_flash = {
.name = "str7x",
.commands = str7x_command_handlers,
.flash_bank_command = str7x_flash_bank_command,
src/flash/nor/str9x.c
+1 -1
View File
@@ -667,7 +667,7 @@ static const struct command_registration str9x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str9x_flash = {
const struct flash_driver str9x_flash = {
.name = "str9x",
.commands = str9x_command_handlers,
.flash_bank_command = str9x_flash_bank_command,
src/flash/nor/str9xpec.c
+1 -1
View File
@@ -1195,7 +1195,7 @@ static const struct command_registration str9xpec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str9xpec_flash = {
const struct flash_driver str9xpec_flash = {
.name = "str9xpec",
.commands = str9xpec_command_handlers,
.flash_bank_command = str9xpec_flash_bank_command,
src/flash/nor/tcl.c
+12 -15
View File
@@ -112,7 +112,7 @@ COMMAND_HANDLER(handle_flash_info_command)
LOG_WARNING("Flash protection check is not implemented.");
command_print(CMD_CTX,
"#%d : %s at 0x%8.8" TARGET_PRIxADDR ", size 0x%8.8" PRIx32
"#%d : %s at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32
", buswidth %i, chipwidth %i",
p->bank_number,
p->driver->name,
@@ -177,7 +177,7 @@ COMMAND_HANDLER(handle_flash_probe_command)
retval = p->driver->probe(p);
if (retval == ERROR_OK)
command_print(CMD_CTX,
"flash '%s' found at 0x%8.8" TARGET_PRIxADDR,
"flash '%s' found at " TARGET_ADDR_FMT,
p->driver->name,
p->base);
} else {
@@ -205,8 +205,8 @@ COMMAND_HANDLER(handle_flash_erase_check_command)
command_print(CMD_CTX, "successfully checked erase state");
else {
command_print(CMD_CTX,
"unknown error when checking erase state of flash bank #%s at 0x%8.8"
TARGET_PRIxADDR,
"unknown error when checking erase state of flash bank #%s at "
TARGET_ADDR_FMT,
CMD_ARGV[0],
p->base);
}
@@ -240,7 +240,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
{
struct flash_bank *p;
int retval = ERROR_OK;
uint32_t address;
target_addr_t address;
uint32_t length;
bool do_pad = false;
bool do_unlock = false;
@@ -263,7 +263,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
if (length <= 0) {
@@ -289,7 +289,8 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
retval = flash_erase_address_range(target, do_pad, address, length);
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")"
command_print(CMD_CTX, "erased address " TARGET_ADDR_FMT " (length %"
PRIi32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
@@ -485,11 +486,7 @@ COMMAND_HANDLER(handle_flash_fill_command)
if (CMD_ARGC != 3)
return ERROR_COMMAND_SYNTAX_ERROR;
#if BUILD_TARGET64
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], address);
#else
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
#endif
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
@@ -1110,7 +1107,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
}
const char *driver_name = CMD_ARGV[0];
struct flash_driver *driver = flash_driver_find_by_name(driver_name);
const struct flash_driver *driver = flash_driver_find_by_name(driver_name);
if (NULL == driver) {
/* no matching flash driver found */
LOG_ERROR("flash driver '%s' not found", driver_name);
@@ -1149,7 +1146,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
int retval;
retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
if (ERROR_OK != retval) {
LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" TARGET_PRIxADDR
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
"; usage: %s", driver_name, c->base, driver->usage);
free(c);
return retval;
@@ -1170,7 +1167,7 @@ COMMAND_HANDLER(handle_flash_banks_command)
unsigned n = 0;
for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) {
LOG_USER("#%d : %s (%s) at 0x%8.8" TARGET_PRIxADDR ", size 0x%8.8" PRIx32 ", "
LOG_USER("#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", "
"buswidth %u, chipwidth %u", p->bank_number,
p->name, p->driver->name, p->base, p->size,
p->bus_width, p->chip_width);
src/flash/nor/tms470.c
+6 -6
View File
@@ -165,8 +165,8 @@ static int tms470_read_part_info(struct flash_bank *bank)
part_name = "TMS470R1A256";
if (bank->base >= 0x00040000) {
LOG_ERROR("No %s flash bank contains base address 0x%08"
TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address "
TARGET_ADDR_FMT ".",
part_name,
bank->base);
return ERROR_FLASH_OPERATION_FAILED;
@@ -205,7 +205,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
sizeof(TMS470R1A288_BANK1_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -245,7 +245,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
sizeof(TMS470R1A384_BANK2_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -901,7 +901,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
tms470_read_part_info(bank);
LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" TARGET_PRIxADDR,
LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
count, bank->base + offset);
/* set GLBCTRL.4 */
@@ -1162,7 +1162,7 @@ FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
return ERROR_OK;
}
struct flash_driver tms470_flash = {
const struct flash_driver tms470_flash = {
.name = "tms470",
.commands = tms470_command_handlers,
.flash_bank_command = tms470_flash_bank_command,
src/flash/nor/virtual.c
+2 -2
View File
@@ -185,7 +185,7 @@ static int virtual_info(struct flash_bank *bank, char *buf, int buf_size)
if (master_bank == NULL)
return ERROR_FLASH_OPERATION_FAILED;
snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" TARGET_PRIxADDR,
snprintf(buf, buf_size, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, master_bank->name, master_bank->base);
return ERROR_OK;
@@ -224,7 +224,7 @@ static int virtual_flash_read(struct flash_bank *bank,
return ERROR_OK;
}
struct flash_driver virtual_flash = {
const struct flash_driver virtual_flash = {
.name = "virtual",
.flash_bank_command = virtual_flash_bank_command,
.erase = virtual_erase,
src/flash/nor/w600.c
+1 -1
View File
@@ -376,7 +376,7 @@ static int get_w600_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver w600_flash = {
const struct flash_driver w600_flash = {
.name = "w600",
.flash_bank_command = w600_flash_bank_command,
.erase = w600_erase,
src/flash/nor/xcf.c
+1 -1
View File
@@ -881,7 +881,7 @@ static const struct command_registration xcf_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xcf_flash = {
const struct flash_driver xcf_flash = {
.name = "xcf",
.usage = NULL,
.commands = xcf_command_handlers,
src/flash/nor/xmc1xxx.c
+2 -2
View File
@@ -305,7 +305,7 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
@@ -534,7 +534,7 @@ static const struct command_registration xmc1xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xmc1xxx_flash = {
const struct flash_driver xmc1xxx_flash = {
.name = "xmc1xxx",
.commands = xmc1xxx_command_handlers,
.flash_bank_command = xmc1xxx_flash_bank_command,
src/flash/nor/xmc4xxx.c
+2 -2
View File
@@ -778,7 +778,7 @@ static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
memcpy(&tmp_buf[start_pad], buffer, remaining);
if (end_pad) {
LOG_INFO("Padding end of page @%08" TARGET_PRIxADDR " by %d bytes",
LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
bank->base + offset, end_pad);
memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
}
@@ -1343,7 +1343,7 @@ static const struct command_registration xmc4xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xmc4xxx_flash = {
const struct flash_driver xmc4xxx_flash = {
.name = "xmc4xxx",
.commands = xmc4xxx_command_handlers,
.flash_bank_command = xmc4xxx_flash_bank_command,
src/helper/command.c
+1 -1
View File
@@ -1037,7 +1037,7 @@ static int command_unknown(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
/* pass the command through to the intended handler */
if (c->jim_handler) {
if (!command_can_run(cmd_ctx, c))
return ERROR_FAIL;
return JIM_ERR;
interp->cmdPrivData = c->jim_handler_data;
return (*c->jim_handler)(interp, count, start);
src/jtag/drivers/cmsis_dap_usb.c
+2 -2
View File
@@ -77,8 +77,8 @@ static bool swd_mode;
#define CMD_DAP_RESET_TARGET 0x0A
/* CMD_INFO */
#define INFO_ID_VID 0x00 /* string */
#define INFO_ID_PID 0x02 /* string */
#define INFO_ID_VENDOR 0x01 /* string */
#define INFO_ID_PRODUCT 0x02 /* string */
#define INFO_ID_SERNUM 0x03 /* string */
#define INFO_ID_FW_VER 0x04 /* string */
#define INFO_ID_TD_VEND 0x05 /* string */
src/jtag/drivers/ftdi.c
+6 -31
View File
@@ -53,11 +53,11 @@
*
* This code uses information contained in the MPSSE specification which was
* found here:
* http://www.ftdichip.com/Documents/AppNotes/AN2232C-01_MPSSE_Cmnd.pdf
* https://www.ftdichip.com/Support/Documents/AppNotes/AN2232C-01_MPSSE_Cmnd.pdf
* Hereafter this is called the "MPSSE Spec".
*
* The datasheet for the ftdichip.com's FT2232D part is here:
* http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf
* The datasheet for the ftdichip.com's FT2232H part is here:
* https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
*
* Also note the issue with code 0x4b (clock data to TMS) noted in
* http://developer.intra2net.com/mailarchive/html/libftdi/2009/msg00292.html
@@ -69,6 +69,7 @@
#endif
/* project specific includes */
#include <jtag/drivers/jtag_usb_common.h>
#include <jtag/interface.h>
#include <jtag/swd.h>
#include <transport/transport.h>
@@ -102,7 +103,6 @@
static char *ftdi_device_desc;
static char *ftdi_serial;
static char *ftdi_location;
static uint8_t ftdi_channel;
static uint8_t ftdi_jtag_mode = JTAG_MODE;
@@ -731,7 +731,7 @@ static int ftdi_initialize(void)
for (int i = 0; ftdi_vid[i] || ftdi_pid[i]; i++) {
mpsse_ctx = mpsse_open(&ftdi_vid[i], &ftdi_pid[i], ftdi_device_desc,
ftdi_serial, ftdi_location, ftdi_channel);
ftdi_serial, jtag_usb_get_location(), ftdi_channel);
if (mpsse_ctx)
break;
}
@@ -788,7 +788,6 @@ static int ftdi_quit(void)
free(ftdi_device_desc);
free(ftdi_serial);
free(ftdi_location);
free(swd_cmd_queue);
@@ -1055,21 +1054,6 @@ COMMAND_HANDLER(ftdi_handle_serial_command)
return ERROR_OK;
}
#ifdef HAVE_LIBUSB_GET_PORT_NUMBERS
COMMAND_HANDLER(ftdi_handle_location_command)
{
if (CMD_ARGC == 1) {
if (ftdi_location)
free(ftdi_location);
ftdi_location = strdup(CMD_ARGV[0]);
} else {
return ERROR_COMMAND_SYNTAX_ERROR;
}
return ERROR_OK;
}
#endif
COMMAND_HANDLER(ftdi_handle_channel_command)
{
if (CMD_ARGC == 1)
@@ -1298,15 +1282,6 @@ static const struct command_registration ftdi_command_handlers[] = {
.help = "set the serial number of the FTDI device",
.usage = "serial_string",
},
#ifdef HAVE_LIBUSB_GET_PORT_NUMBERS
{
.name = "ftdi_location",
.handler = &ftdi_handle_location_command,
.mode = COMMAND_CONFIG,
.help = "set the USB bus location of the FTDI device",
.usage = "<bus>:port[,port]...",
},
#endif
{
.name = "ftdi_channel",
.handler = &ftdi_handle_channel_command,
@@ -1421,7 +1396,7 @@ static void ftdi_swd_swdio_en(bool enable)
if (oe->data_mask)
ftdi_set_signal(oe, enable ? '1' : '0');
else {
/* Sets TDI/DO pin (pin 2) to input during rx when both pins are connected
/* Sets TDI/DO pin to input during rx when both pins are connected
to SWDIO */
if (enable)
direction |= jtag_direction_init & 0x0002U;
src/jtag/drivers/stlink_usb.c
+102 -70
View File
@@ -156,6 +156,7 @@ struct stlink_usb_handle_s {
#define STLINK_SWD_AP_FAULT 0x11
#define STLINK_SWD_AP_ERROR 0x12
#define STLINK_SWD_AP_PARITY_ERROR 0x13
#define STLINK_JTAG_GET_IDCODE_ERROR 0x09
#define STLINK_JTAG_WRITE_ERROR 0x0c
#define STLINK_JTAG_WRITE_VERIF_ERROR 0x0d
#define STLINK_SWD_DP_WAIT 0x14
@@ -167,6 +168,8 @@ struct stlink_usb_handle_s {
#define STLINK_SWD_AP_STICKY_ERROR 0x19
#define STLINK_SWD_AP_STICKYORUN_ERROR 0x1a
#define STLINK_BAD_AP_ERROR 0x1d
#define STLINK_CORE_RUNNING 0x80
#define STLINK_CORE_HALTED 0x81
#define STLINK_CORE_STAT_UNKNOWN -1
@@ -341,6 +344,9 @@ static const struct speed_map stlink_khz_to_speed_map_jtag[] = {
static void stlink_usb_init_buffer(void *handle, uint8_t direction, uint32_t size);
static int stlink_swim_status(void *handle);
void stlink_dump_speed_map(const struct speed_map *map, unsigned int map_size);
static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map);
static int stlink_speed(void *handle, int khz, bool query);
/** */
static unsigned int stlink_usb_block(void *handle)
@@ -640,8 +646,9 @@ static int stlink_usb_xfer_v1_get_sense(void *handle)
transfers block in cmdbuf
<size> indicates number of bytes in the following
data phase.
Ignore the (eventual) error code in the received packet.
*/
static int stlink_usb_xfer(void *handle, const uint8_t *buf, int size)
static int stlink_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, int size)
{
int err, cmdsize = STLINK_CMD_SIZE_V2;
struct stlink_usb_handle_s *h = handle;
@@ -712,6 +719,9 @@ static int stlink_usb_error_check(void *handle)
case STLINK_SWD_DP_WAIT:
LOG_DEBUG("wait status SWD_DP_WAIT (0x%x)", STLINK_SWD_DP_WAIT);
return ERROR_WAIT;
case STLINK_JTAG_GET_IDCODE_ERROR:
LOG_DEBUG("STLINK_JTAG_GET_IDCODE_ERROR");
return ERROR_FAIL;
case STLINK_JTAG_WRITE_ERROR:
LOG_DEBUG("Write error");
return ERROR_FAIL;
@@ -750,12 +760,31 @@ static int stlink_usb_error_check(void *handle)
case STLINK_SWD_AP_STICKYORUN_ERROR:
LOG_DEBUG("STLINK_SWD_AP_STICKYORUN_ERROR");
return ERROR_FAIL;
case STLINK_BAD_AP_ERROR:
LOG_DEBUG("STLINK_BAD_AP_ERROR");
return ERROR_FAIL;
default:
LOG_DEBUG("unknown/unexpected STLINK status code 0x%x", h->databuf[0]);
return ERROR_FAIL;
}
}
/*
* Wrapper around stlink_usb_xfer_noerrcheck()
* to check the error code in the received packet
*/
static int stlink_usb_xfer_errcheck(void *handle, const uint8_t *buf, int size)
{
int retval;
assert(size > 0);
retval = stlink_usb_xfer_noerrcheck(handle, buf, size);
if (retval != ERROR_OK)
return retval;
return stlink_usb_error_check(handle);
}
/** Issue an STLINK command via USB transfer, with retries on any wait status responses.
@@ -772,7 +801,7 @@ static int stlink_cmd_allow_retry(void *handle, const uint8_t *buf, int size)
while (1) {
if ((h->transport != HL_TRANSPORT_SWIM) || !retries) {
res = stlink_usb_xfer(handle, buf, size);
res = stlink_usb_xfer_noerrcheck(handle, buf, size);
if (res != ERROR_OK)
return res;
}
@@ -876,7 +905,7 @@ static int stlink_usb_version(void *handle)
h->cmdbuf[h->cmdidx++] = STLINK_GET_VERSION;
res = stlink_usb_xfer(handle, h->databuf, 6);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 6);
if (res != ERROR_OK)
return res;
@@ -917,7 +946,7 @@ static int stlink_usb_version(void *handle)
h->cmdbuf[h->cmdidx++] = STLINK_APIV3_GET_VERSION_EX;
res = stlink_usb_xfer(handle, h->databuf, 12);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 12);
if (res != ERROR_OK)
return res;
@@ -1001,7 +1030,7 @@ static int stlink_usb_version(void *handle)
if (bridge)
p += sprintf(p, "B%d", bridge);
if (swim || !msd)
p += sprintf(p, "S%d", swim);
sprintf(p, "S%d", swim);
LOG_INFO("STLINK %s (API v%d) VID:PID %04X:%04X",
v_str,
@@ -1025,7 +1054,7 @@ static int stlink_usb_check_voltage(void *handle, float *target_voltage)
h->cmdbuf[h->cmdidx++] = STLINK_GET_TARGET_VOLTAGE;
int result = stlink_usb_xfer(handle, h->databuf, 8);
int result = stlink_usb_xfer_noerrcheck(handle, h->databuf, 8);
if (result != ERROR_OK)
return result;
@@ -1104,7 +1133,7 @@ static int stlink_usb_current_mode(void *handle, uint8_t *mode)
h->cmdbuf[h->cmdidx++] = STLINK_GET_CURRENT_MODE;
res = stlink_usb_xfer(handle, h->databuf, 2);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 2);
if (res != ERROR_OK)
return res;
@@ -1192,7 +1221,7 @@ static int stlink_usb_mode_leave(void *handle, enum stlink_mode type)
return ERROR_FAIL;
}
res = stlink_usb_xfer(handle, 0, 0);
res = stlink_usb_xfer_noerrcheck(handle, 0, 0);
if (res != ERROR_OK)
return res;
@@ -1217,7 +1246,7 @@ static enum stlink_mode stlink_get_mode(enum hl_transports t)
}
/** */
static int stlink_usb_init_mode(void *handle, bool connect_under_reset)
static int stlink_usb_init_mode(void *handle, bool connect_under_reset, int initial_interface_speed)
{
int res;
uint8_t mode;
@@ -1296,6 +1325,27 @@ static int stlink_usb_init_mode(void *handle, bool connect_under_reset)
return ERROR_FAIL;
}
/* set the speed before entering the mode, as the chip discovery phase should be done at this speed too */
if (h->transport == HL_TRANSPORT_JTAG) {
if (h->version.flags & STLINK_F_HAS_JTAG_SET_FREQ) {
stlink_dump_speed_map(stlink_khz_to_speed_map_jtag, ARRAY_SIZE(stlink_khz_to_speed_map_jtag));
stlink_speed(h, initial_interface_speed, false);
}
} else if (h->transport == HL_TRANSPORT_SWD) {
if (h->version.flags & STLINK_F_HAS_SWD_SET_FREQ) {
stlink_dump_speed_map(stlink_khz_to_speed_map_swd, ARRAY_SIZE(stlink_khz_to_speed_map_swd));
stlink_speed(h, initial_interface_speed, false);
}
}
if (h->version.jtag_api == STLINK_JTAG_API_V3) {
struct speed_map map[STLINK_V3_MAX_FREQ_NB];
stlink_get_com_freq(h, (h->transport == HL_TRANSPORT_JTAG), map);
stlink_dump_speed_map(map, ARRAY_SIZE(map));
stlink_speed(h, initial_interface_speed, false);
}
/* preliminary SRST assert:
* We want SRST is asserted before activating debug signals (mode_enter).
* As the required mode has not been set, the adapter may not know what pin to use.
@@ -1338,7 +1388,8 @@ static int stlink_swim_status(void *handle)
stlink_usb_init_buffer(handle, h->rx_ep, 4);
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_READSTATUS;
res = stlink_usb_xfer(handle, h->databuf, 4);
/* error is checked by the caller */
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 4);
if (res != ERROR_OK)
return res;
return ERROR_OK;
@@ -1358,7 +1409,7 @@ static int stlink_swim_cap(void *handle, uint8_t *cap)
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_READ_CAP;
h->cmdbuf[h->cmdidx++] = 0x01;
res = stlink_usb_xfer(handle, h->databuf, 8);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 8);
if (res != ERROR_OK)
return res;
memcpy(cap, h->databuf, 8);
@@ -1515,7 +1566,7 @@ static int stlink_swim_readbytes(void *handle, uint32_t addr, uint32_t len, uint
stlink_usb_init_buffer(handle, h->rx_ep, len);
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_SWIM_READBUF;
res = stlink_usb_xfer(handle, data, len);
res = stlink_usb_xfer_noerrcheck(handle, data, len);
if (res != ERROR_OK)
return res;
@@ -1525,7 +1576,7 @@ static int stlink_swim_readbytes(void *handle, uint32_t addr, uint32_t len, uint
/** */
static int stlink_usb_idcode(void *handle, uint32_t *idcode)
{
int res;
int res, offset;
struct stlink_usb_handle_s *h = handle;
assert(handle != NULL);
@@ -1536,17 +1587,25 @@ static int stlink_usb_idcode(void *handle, uint32_t *idcode)
return ERROR_OK;
}
stlink_usb_init_buffer(handle, h->rx_ep, 4);
stlink_usb_init_buffer(handle, h->rx_ep, 12);
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_READCOREID;
if (h->version.jtag_api == STLINK_JTAG_API_V1) {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_READCOREID;
res = stlink_usb_xfer(handle, h->databuf, 4);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 4);
offset = 0;
} else {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_READ_IDCODES;
res = stlink_usb_xfer_errcheck(handle, h->databuf, 12);
offset = 4;
}
if (res != ERROR_OK)
return res;
*idcode = le_to_h_u32(h->databuf);
*idcode = le_to_h_u32(h->databuf + offset);
LOG_DEBUG("IDCODE: 0x%08" PRIX32, *idcode);
@@ -1611,7 +1670,7 @@ static int stlink_usb_trace_read(void *handle, uint8_t *buf, size_t *size)
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_GET_TRACE_NB;
res = stlink_usb_xfer(handle, h->databuf, 2);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 2);
if (res != ERROR_OK)
return res;
@@ -1688,7 +1747,7 @@ static enum target_state stlink_usb_state(void *handle)
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_GETSTATUS;
res = stlink_usb_xfer(handle, h->databuf, 2);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 2);
if (res != ERROR_OK)
return TARGET_UNKNOWN;
@@ -1739,7 +1798,7 @@ static void stlink_usb_trace_disable(void *handle)
stlink_usb_init_buffer(handle, h->rx_ep, 2);
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX;
res = stlink_usb_xfer(handle, h->databuf, 2);
res = stlink_usb_xfer_errcheck(handle, h->databuf, 2);
if (res == ERROR_OK)
h->trace.enabled = false;
@@ -1764,7 +1823,7 @@ static int stlink_usb_trace_enable(void *handle)
h_u32_to_le(h->cmdbuf+h->cmdidx, h->trace.source_hz);
h->cmdidx += 4;
res = stlink_usb_xfer(handle, h->databuf, 2);
res = stlink_usb_xfer_errcheck(handle, h->databuf, 2);
if (res == ERROR_OK) {
h->trace.enabled = true;
@@ -1885,20 +1944,21 @@ static int stlink_usb_read_regs(void *handle)
assert(handle != NULL);
stlink_usb_init_buffer(handle, h->rx_ep, 84);
stlink_usb_init_buffer(handle, h->rx_ep, 88);
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
if (h->version.jtag_api == STLINK_JTAG_API_V1)
if (h->version.jtag_api == STLINK_JTAG_API_V1) {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV1_READALLREGS;
else
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 84);
/* regs data from offset 0 */
} else {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_READALLREGS;
res = stlink_usb_xfer_errcheck(handle, h->databuf, 88);
/* status at offset 0, regs data from offset 4 */
}
res = stlink_usb_xfer(handle, h->databuf, 84);
if (res != ERROR_OK)
return res;
return ERROR_OK;
return res;
}
/** */
@@ -1919,7 +1979,7 @@ static int stlink_usb_read_reg(void *handle, int num, uint32_t *val)
h->cmdbuf[h->cmdidx++] = num;
if (h->version.jtag_api == STLINK_JTAG_API_V1) {
res = stlink_usb_xfer(handle, h->databuf, 4);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, 4);
if (res != ERROR_OK)
return res;
*val = le_to_h_u32(h->databuf);
@@ -1956,7 +2016,6 @@ static int stlink_usb_write_reg(void *handle, int num, uint32_t val)
static int stlink_usb_get_rw_status(void *handle)
{
int res;
struct stlink_usb_handle_s *h = handle;
assert(handle != NULL);
@@ -1969,18 +2028,11 @@ static int stlink_usb_get_rw_status(void *handle)
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_COMMAND;
if (h->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2;
res = stlink_usb_xfer(handle, h->databuf, 12);
return stlink_usb_xfer_errcheck(handle, h->databuf, 12);
} else {
h->cmdbuf[h->cmdidx++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS;
res = stlink_usb_xfer(handle, h->databuf, 2);
return stlink_usb_xfer_errcheck(handle, h->databuf, 2);
}
if (res != ERROR_OK)
return res;
return stlink_usb_error_check(h);
}
/** */
@@ -2012,7 +2064,7 @@ static int stlink_usb_read_mem8(void *handle, uint32_t addr, uint16_t len,
if (read_len == 1)
read_len++;
res = stlink_usb_xfer(handle, h->databuf, read_len);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, read_len);
if (res != ERROR_OK)
return res;
@@ -2046,7 +2098,7 @@ static int stlink_usb_write_mem8(void *handle, uint32_t addr, uint16_t len,
h_u16_to_le(h->cmdbuf+h->cmdidx, len);
h->cmdidx += 2;
res = stlink_usb_xfer(handle, buffer, len);
res = stlink_usb_xfer_noerrcheck(handle, buffer, len);
if (res != ERROR_OK)
return res;
@@ -2081,7 +2133,7 @@ static int stlink_usb_read_mem16(void *handle, uint32_t addr, uint16_t len,
h_u16_to_le(h->cmdbuf+h->cmdidx, len);
h->cmdidx += 2;
res = stlink_usb_xfer(handle, h->databuf, len);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, len);
if (res != ERROR_OK)
return res;
@@ -2118,7 +2170,7 @@ static int stlink_usb_write_mem16(void *handle, uint32_t addr, uint16_t len,
h_u16_to_le(h->cmdbuf+h->cmdidx, len);
h->cmdidx += 2;
res = stlink_usb_xfer(handle, buffer, len);
res = stlink_usb_xfer_noerrcheck(handle, buffer, len);
if (res != ERROR_OK)
return res;
@@ -2150,7 +2202,7 @@ static int stlink_usb_read_mem32(void *handle, uint32_t addr, uint16_t len,
h_u16_to_le(h->cmdbuf+h->cmdidx, len);
h->cmdidx += 2;
res = stlink_usb_xfer(handle, h->databuf, len);
res = stlink_usb_xfer_noerrcheck(handle, h->databuf, len);
if (res != ERROR_OK)
return res;
@@ -2184,7 +2236,7 @@ static int stlink_usb_write_mem32(void *handle, uint32_t addr, uint16_t len,
h_u16_to_le(h->cmdbuf+h->cmdidx, len);
h->cmdidx += 2;
res = stlink_usb_xfer(handle, buffer, len);
res = stlink_usb_xfer_noerrcheck(handle, buffer, len);
if (res != ERROR_OK)
return res;
@@ -2505,7 +2557,7 @@ static int stlink_get_com_freq(void *handle, bool is_jtag, struct speed_map *map
h->cmdbuf[h->cmdidx++] = STLINK_APIV3_GET_COM_FREQ;
h->cmdbuf[h->cmdidx++] = is_jtag ? 1 : 0;
int res = stlink_usb_xfer(handle, h->databuf, 52);
int res = stlink_usb_xfer_errcheck(handle, h->databuf, 52);
int size = h->databuf[8];
@@ -2542,7 +2594,7 @@ static int stlink_set_com_freq(void *handle, bool is_jtag, unsigned int frequenc
h_u32_to_le(&h->cmdbuf[4], frequency);
return stlink_usb_xfer(handle, h->databuf, 8);
return stlink_usb_xfer_errcheck(handle, h->databuf, 8);
}
static int stlink_speed_v3(void *handle, bool is_jtag, int khz, bool query)
@@ -2785,7 +2837,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
}
/* initialize the debug hardware */
err = stlink_usb_init_mode(h, param->connect_under_reset);
err = stlink_usb_init_mode(h, param->connect_under_reset, param->initial_interface_speed);
if (err != ERROR_OK) {
LOG_ERROR("init mode failed (unable to connect to the target)");
@@ -2803,26 +2855,6 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
return ERROR_OK;
}
if (h->transport == HL_TRANSPORT_JTAG) {
if (h->version.flags & STLINK_F_HAS_JTAG_SET_FREQ) {
stlink_dump_speed_map(stlink_khz_to_speed_map_jtag, ARRAY_SIZE(stlink_khz_to_speed_map_jtag));
stlink_speed(h, param->initial_interface_speed, false);
}
} else if (h->transport == HL_TRANSPORT_SWD) {
if (h->version.flags & STLINK_F_HAS_SWD_SET_FREQ) {
stlink_dump_speed_map(stlink_khz_to_speed_map_swd, ARRAY_SIZE(stlink_khz_to_speed_map_swd));
stlink_speed(h, param->initial_interface_speed, false);
}
}
if (h->version.jtag_api == STLINK_JTAG_API_V3) {
struct speed_map map[STLINK_V3_MAX_FREQ_NB];
stlink_get_com_freq(h, (h->transport == HL_TRANSPORT_JTAG), map);
stlink_dump_speed_map(map, ARRAY_SIZE(map));
stlink_speed(h, param->initial_interface_speed, false);
}
/* get cpuid, so we can determine the max page size
* start with a safe default */
h->max_mem_packet = (1 << 10);
src/rtos/hwthread.c
+1 -1
View File
@@ -199,6 +199,7 @@ static int hwthread_update_threads(struct rtos *rtos)
else
rtos->current_thread = threadid_from_target(target);
LOG_DEBUG("%s current_thread=%i", __func__, (int)rtos->current_thread);
return 0;
}
@@ -367,7 +368,6 @@ static int hwthread_thread_packet(struct connection *connection, const char *pac
target->rtos->current_thread = threadid_from_target(target);
target->rtos->current_threadid = current_threadid;
LOG_DEBUG("current_threadid=%" PRId64, current_threadid);
gdb_put_packet(connection, "OK", 2);
return ERROR_OK;
src/server/gdb_server.c
+7 -5
View File
@@ -153,6 +153,8 @@ static int gdb_last_signal(struct target *target)
return 0x05; /* SIGTRAP */
case DBG_REASON_SINGLESTEP:
return 0x05; /* SIGTRAP */
case DBG_REASON_EXC_CATCH:
return 0x05;
case DBG_REASON_NOTHALTED:
return 0x0; /* no signal... shouldn't happen */
default:
@@ -1450,7 +1452,7 @@ static int gdb_read_memory_packet(struct connection *connection,
if (!len) {
LOG_WARNING("invalid read memory packet received (len == 0)");
gdb_put_packet(connection, NULL, 0);
gdb_put_packet(connection, "", 0);
return ERROR_OK;
}
@@ -1935,7 +1937,7 @@ static int gdb_memory_map(struct connection *connection,
xml_printf(&retval, &xml, &pos, &size,
"<memory type=\"ram\" start=\"" TARGET_ADDR_FMT "\" "
"length=\"" TARGET_ADDR_FMT "\"/>\n",
ram_start, TARGET_ADDR_MAX - ram_start + 1);
ram_start, target_address_max(target) - ram_start + 1);
/* ELSE a flash chip could be at the very end of the address space, in
* which case ram_start will be precisely 0 */
@@ -2863,7 +2865,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
if (gdb_connection->sync) {
gdb_connection->sync = false;
if (ct->state == TARGET_HALTED) {
LOG_WARNING("stepi ignored. GDB will now fetch the register state " \
LOG_DEBUG("stepi ignored. GDB will now fetch the register state " \
"from the target.");
gdb_sig_halted(connection);
log_remove_callback(gdb_log_callback, connection);
@@ -3251,7 +3253,7 @@ static int gdb_input_inner(struct connection *connection)
* make only the single stepping have the sync feature...
*/
nostep = true;
LOG_WARNING("stepi ignored. GDB will now fetch the register state " \
LOG_DEBUG("stepi ignored. GDB will now fetch the register state " \
"from the target.");
}
gdb_con->sync = false;
@@ -3354,7 +3356,7 @@ static int gdb_input_inner(struct connection *connection)
default:
/* ignore unknown packets */
LOG_DEBUG("ignoring 0x%2.2x packet", packet[0]);
gdb_put_packet(connection, NULL, 0);
gdb_put_packet(connection, "", 0);
break;
}
src/server/server.c
+2
View File
@@ -703,6 +703,8 @@ void server_free(void)
tcl_service_free();
telnet_service_free();
jsp_service_free();
free(bindto_name);
}
void exit_on_signal(int sig)
src/target/aarch64.c
+15 -56
View File
@@ -29,6 +29,7 @@
#include "armv8_opcodes.h"
#include "armv8_cache.h"
#include "arm_semihosting.h"
#include "smp.h"
#include <helper/time_support.h>
enum restart_mode {
@@ -63,9 +64,6 @@ static int aarch64_virt2phys(struct target *target,
static int aarch64_read_cpu_memory(struct target *target,
uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
#define foreach_smp_target(pos, head) \
for (pos = head; (pos != NULL); pos = pos->next)
static int aarch64_restore_system_control_reg(struct target *target)
{
enum arm_mode target_mode = ARM_MODE_ANY;
@@ -601,8 +599,8 @@ static int aarch64_restore_one(struct target *target, int current,
}
LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc);
buf_set_u64(arm->pc->value, 0, 64, resume_pc);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
/* called it now before restoring context because it uses cpu
* register r0 for restoring system control register */
@@ -2388,7 +2386,8 @@ static int aarch64_init_arch_info(struct target *target,
armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory;
armv8_init_arch_info(target, armv8);
target_register_timer_callback(aarch64_handle_target_request, 1, 1, target);
target_register_timer_callback(aarch64_handle_target_request, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
@@ -2396,11 +2395,17 @@ static int aarch64_init_arch_info(struct target *target,
static int aarch64_target_create(struct target *target, Jim_Interp *interp)
{
struct aarch64_private_config *pc = target->private_config;
struct aarch64_common *aarch64 = calloc(1, sizeof(struct aarch64_common));
struct aarch64_common *aarch64;
if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
return ERROR_FAIL;
aarch64 = calloc(1, sizeof(struct aarch64_common));
if (aarch64 == NULL) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
}
@@ -2543,42 +2548,6 @@ COMMAND_HANDLER(aarch64_handle_dbginit_command)
return aarch64_init_debug_access(target);
}
COMMAND_HANDLER(aarch64_handle_smp_off_command)
{
struct target *target = get_current_target(CMD_CTX);
/* check target is an smp target */
struct target_list *head;
struct target *curr;
head = target->head;
target->smp = 0;
if (head != (struct target_list *)NULL) {
while (head != (struct target_list *)NULL) {
curr = head->target;
curr->smp = 0;
head = head->next;
}
/* fixes the target display to the debugger */
target->gdb_service->target = target;
}
return ERROR_OK;
}
COMMAND_HANDLER(aarch64_handle_smp_on_command)
{
struct target *target = get_current_target(CMD_CTX);
struct target_list *head;
struct target *curr;
head = target->head;
if (head != (struct target_list *)NULL) {
target->smp = 1;
while (head != (struct target_list *)NULL) {
curr = head->target;
curr->smp = 1;
head = head->next;
}
}
return ERROR_OK;
}
COMMAND_HANDLER(aarch64_mask_interrupts_command)
{
@@ -2760,19 +2729,6 @@ static const struct command_registration aarch64_exec_command_handlers[] = {
.help = "Initialize core debug",
.usage = "",
},
{ .name = "smp_off",
.handler = aarch64_handle_smp_off_command,
.mode = COMMAND_EXEC,
.help = "Stop smp handling",
.usage = "",
},
{
.name = "smp_on",
.handler = aarch64_handle_smp_on_command,
.mode = COMMAND_EXEC,
.help = "Restart smp handling",
.usage = "",
},
{
.name = "maskisr",
.handler = aarch64_mask_interrupts_command,
@@ -2794,6 +2750,9 @@ static const struct command_registration aarch64_exec_command_handlers[] = {
.help = "read coprocessor register",
.usage = "cpnum op1 CRn CRm op2",
},
{
.chain = smp_command_handlers,
},
COMMAND_REGISTRATION_DONE
src/target/adi_v5_swd.c
+43 -11
View File
@@ -166,22 +166,26 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
}
/** Select the DP register bank matching bits 7:4 of reg. */
static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
{
/* Only register address 4 is banked. */
if ((reg & 0xf) != 4)
return;
return ERROR_OK;
uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
uint32_t sel = select_dp_bank
| (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
if (sel == dap->select)
return;
return ERROR_OK;
dap->select = sel;
swd_queue_dp_write(dap, DP_SELECT, sel);
int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
if (retval != ERROR_OK)
dap->select = DP_SELECT_INVALID;
return retval;
}
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
@@ -194,7 +198,10 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
if (retval != ERROR_OK)
return retval;
swd_queue_dp_bankselect(dap, reg);
retval = swd_queue_dp_bankselect(dap, reg);
if (retval != ERROR_OK)
return retval;
swd->read_reg(swd_cmd(true, false, reg), data, 0);
return check_sync(dap);
@@ -211,14 +218,29 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
return retval;
swd_finish_read(dap);
swd_queue_dp_bankselect(dap, reg);
if (reg == DP_SELECT) {
dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
swd->write_reg(swd_cmd(false, false, reg), data, 0);
retval = check_sync(dap);
if (retval != ERROR_OK)
dap->select = DP_SELECT_INVALID;
return retval;
}
retval = swd_queue_dp_bankselect(dap, reg);
if (retval != ERROR_OK)
return retval;
swd->write_reg(swd_cmd(false, false, reg), data, 0);
return check_sync(dap);
}
/** Select the AP register bank matching bits 7:4 of reg. */
static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
{
struct adiv5_dap *dap = ap->dap;
uint32_t sel = ((uint32_t)ap->ap_num << 24)
@@ -226,11 +248,15 @@ static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
| (dap->select & DP_SELECT_DPBANK);
if (sel == dap->select)
return;
return ERROR_OK;
dap->select = sel;
swd_queue_dp_write(dap, DP_SELECT, sel);
int retval = swd_queue_dp_write(dap, DP_SELECT, sel);
if (retval != ERROR_OK)
dap->select = DP_SELECT_INVALID;
return retval;
}
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
@@ -244,7 +270,10 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
if (retval != ERROR_OK)
return retval;
swd_queue_ap_bankselect(ap, reg);
retval = swd_queue_ap_bankselect(ap, reg);
if (retval != ERROR_OK)
return retval;
swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
dap->last_read = data;
@@ -263,7 +292,10 @@ static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
return retval;
swd_finish_read(dap);
swd_queue_ap_bankselect(ap, reg);
retval = swd_queue_ap_bankselect(ap, reg);
if (retval != ERROR_OK)
return retval;
swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
return check_sync(dap);
src/target/arm11.c
+2 -2
View File
@@ -442,8 +442,8 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t a
}
buf_set_u32(value, 0, 32, address);
arm11->arm.pc->dirty = 1;
arm11->arm.pc->valid = 1;
arm11->arm.pc->dirty = true;
arm11->arm.pc->valid = true;
return address;
}
src/target/arm720t.c
+3 -3
View File
@@ -365,12 +365,12 @@ static int arm720t_soft_reset_halt(struct target *target)
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
src/target/arm7_9_common.c
+35 -35
View File
@@ -1141,20 +1141,20 @@ int arm7_9_soft_reset_halt(struct target *target)
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
/* reset registers */
for (i = 0; i <= 14; i++) {
struct reg *r = arm_reg_current(arm, i);
buf_set_u32(r->value, 0, 32, 0xffffffff);
r->dirty = 1;
r->valid = 1;
r->dirty = true;
r->valid = true;
}
retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1346,7 +1346,7 @@ static int arm7_9_debug_entry(struct target *target)
buf_set_u32(r->value, 0, 32, context[i]);
/* r0 and r15 (pc) have to be restored later */
r->dirty = (i == 0) || (i == 15);
r->valid = 1;
r->valid = true;
}
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
@@ -1359,8 +1359,8 @@ static int arm7_9_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
buf_set_u32(arm->spsr->value, 0, 32, spsr);
arm->spsr->dirty = 0;
arm->spsr->valid = 1;
arm->spsr->dirty = false;
arm->spsr->valid = true;
}
retval = jtag_execute_queue();
@@ -1411,13 +1411,13 @@ static int arm7_9_full_context(struct target *target)
uint32_t mask = 0;
uint32_t *reg_p[16];
int j;
int valid = 1;
bool valid = true;
/* check if there are invalid registers in the current mode
*/
for (j = 0; j <= 16; j++) {
if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
valid = 0;
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid)
valid = false;
}
if (!valid) {
@@ -1431,8 +1431,8 @@ static int arm7_9_full_context(struct target *target)
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
for (j = 0; j < 15; j++) {
if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i), j).valid == 0) {
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i), j).valid) {
reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(
arm->core_cache,
armv4_5_number_to_mode(i),
@@ -1440,10 +1440,10 @@ static int arm7_9_full_context(struct target *target)
mask |= 1 << j;
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i),
j).valid = 1;
j).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i),
j).dirty = 0;
j).dirty = false;
}
}
@@ -1452,15 +1452,15 @@ static int arm7_9_full_context(struct target *target)
arm7_9->read_core_regs(target, mask, reg_p);
/* check if the PSR has to be read */
if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).valid == 0) {
if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).valid) {
arm7_9->read_xpsr(target,
(uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
armv4_5_number_to_mode(i), 16).value, 1);
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).valid = 1;
16).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
16).dirty = 0;
16).dirty = false;
}
}
}
@@ -1494,7 +1494,7 @@ static int arm7_9_restore_context(struct target *target)
struct reg *reg;
enum arm_mode current_mode = arm->core_mode;
int i, j;
int dirty;
bool dirty;
int mode_change;
LOG_DEBUG("-");
@@ -1518,15 +1518,15 @@ static int arm7_9_restore_context(struct target *target)
for (i = 0; i < 6; i++) {
LOG_DEBUG("examining %s mode",
arm_mode_name(arm->core_mode));
dirty = 0;
dirty = false;
mode_change = 0;
/* check if there are dirty registers in the current mode
*/
for (j = 0; j <= 16; j++) {
reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
if (reg->dirty == 1) {
if (reg->valid == 1) {
dirty = 1;
if (reg->dirty) {
if (reg->valid) {
dirty = true;
LOG_DEBUG("examining dirty reg: %s", reg->name);
struct arm_reg *reg_arch_info;
reg_arch_info = reg->arch_info;
@@ -1567,12 +1567,12 @@ static int arm7_9_restore_context(struct target *target)
armv4_5_number_to_mode(i),
j);
if (reg->dirty == 1) {
if (reg->dirty) {
regs[j] = buf_get_u32(reg->value, 0, 32);
mask |= 1 << j;
num_regs++;
reg->dirty = 0;
reg->valid = 1;
reg->dirty = false;
reg->valid = true;
LOG_DEBUG("writing register %i mode %s "
"with value 0x%8.8" PRIx32, j,
arm_mode_name(arm->core_mode),
@@ -1614,15 +1614,15 @@ static int arm7_9_restore_context(struct target *target)
arm7_9->write_xpsr(target,
buf_get_u32(arm->cpsr->value, 0, 32)
& ~0x20, 0);
arm->cpsr->dirty = 0;
arm->cpsr->valid = 1;
arm->cpsr->dirty = false;
arm->cpsr->valid = true;
}
/* restore PC */
LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32));
arm->pc->dirty = 0;
arm->pc->dirty = false;
return ERROR_OK;
}
@@ -2024,8 +2024,8 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
if (retval != ERROR_OK)
return retval;
r->valid = 1;
r->dirty = 0;
r->valid = true;
r->dirty = false;
buf_set_u32(r->value, 0, 32, value);
if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
@@ -2081,8 +2081,8 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
arm7_9->write_xpsr(target, t, spsr);
}
r->valid = 1;
r->dirty = 0;
r->valid = true;
r->dirty = false;
if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
&& (areg->mode != ARM_MODE_ANY)) {
@@ -2859,7 +2859,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,
1, 1, target);
1, TARGET_TIMER_TYPE_PERIODIC, target);
}
static const struct command_registration arm7_9_any_command_handlers[] = {
src/target/arm920t.c
+7 -7
View File
@@ -283,8 +283,8 @@ static int arm920t_read_cp15_interpreted(struct target *target,
return ERROR_FAIL;
}
r[0].dirty = 1;
r[1].dirty = 1;
r[0].dirty = true;
r[1].dirty = true;
return ERROR_OK;
}
@@ -327,8 +327,8 @@ int arm920t_write_cp15_interpreted(struct target *target,
return ERROR_FAIL;
}
r[0].dirty = 1;
r[1].dirty = 1;
r[0].dirty = true;
r[1].dirty = true;
return ERROR_OK;
}
@@ -781,12 +781,12 @@ int arm920t_soft_reset_halt(struct target *target)
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
arm920t_disable_mmu_caches(target, 1, 1, 1);
arm920t->armv4_5_mmu.mmu_enabled = 0;
src/target/arm926ejs.c
+3 -3
View File
@@ -576,12 +576,12 @@ int arm926ejs_soft_reset_halt(struct target *target)
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
src/target/arm_semihosting.c
+6 -6
View File
@@ -94,12 +94,12 @@ static int post_result(struct target *target)
/* return value in R0 */
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm->core_cache->reg_list[0].dirty = 1;
arm->core_cache->reg_list[0].dirty = true;
/* LR --> PC */
buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
buf_get_u32(arm_reg_current(arm, 14)->value, 0, 32));
arm->core_cache->reg_list[15].dirty = 1;
arm->core_cache->reg_list[15].dirty = true;
/* saved PSR --> current PSR */
spsr = buf_get_u32(arm->spsr->value, 0, 32);
@@ -109,7 +109,7 @@ static int post_result(struct target *target)
*/
buf_set_u32(arm->cpsr->value, 0, 32, spsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
arm->core_mode = spsr & 0x1f;
if (spsr & 0x20)
arm->core_state = ARM_STATE_THUMB;
@@ -118,11 +118,11 @@ static int post_result(struct target *target)
if (arm->core_state == ARM_STATE_AARCH64) {
/* return value in R0 */
buf_set_u64(arm->core_cache->reg_list[0].value, 0, 64, target->semihosting->result);
arm->core_cache->reg_list[0].dirty = 1;
arm->core_cache->reg_list[0].dirty = true;
uint64_t pc = buf_get_u64(arm->core_cache->reg_list[32].value, 0, 64);
buf_set_u64(arm->pc->value, 0, 64, pc + 4);
arm->pc->dirty = 1;
arm->pc->dirty = true;
}
} else {
/* resume execution, this will be pc+2 to skip over the
@@ -130,7 +130,7 @@ static int post_result(struct target *target)
/* return result in R0 */
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result);
arm->core_cache->reg_list[0].dirty = 1;
arm->core_cache->reg_list[0].dirty = true;
}
return ERROR_OK;
src/target/armv4_5.c
+13 -13
View File
@@ -434,8 +434,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
*/
if (arm->cpsr) {
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
arm->cpsr->valid = 1;
arm->cpsr->dirty = 0;
arm->cpsr->valid = true;
arm->cpsr->dirty = false;
}
arm->core_mode = mode;
@@ -526,7 +526,7 @@ static struct reg_feature arm_gdb_dummy_fp_features = {
struct reg arm_gdb_dummy_fp_reg = {
.name = "GDB dummy FPA register",
.value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = 1,
.valid = true,
.size = 96,
.exist = false,
.number = 16,
@@ -543,7 +543,7 @@ static const uint8_t arm_gdb_dummy_fps_value[4];
struct reg arm_gdb_dummy_fps_reg = {
.name = "GDB dummy FPA status register",
.value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = 1,
.valid = true,
.size = 32,
.exist = false,
.number = 24,
@@ -573,8 +573,8 @@ static int armv4_5_get_core_reg(struct reg *reg)
retval = reg_arch_info->arm->read_core_reg(target, reg,
reg_arch_info->num, reg_arch_info->mode);
if (retval == ERROR_OK) {
reg->valid = 1;
reg->dirty = 0;
reg->valid = true;
reg->dirty = false;
}
return retval;
@@ -619,9 +619,9 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
value = buf_get_u32(buf + 4, 0, 32);
buf_set_u32(reg->value + 4, 0, 32, value);
}
reg->valid = 1;
reg->valid = true;
}
reg->dirty = 1;
reg->dirty = true;
return ERROR_OK;
}
@@ -1399,8 +1399,8 @@ int armv4_5_run_algorithm_inner(struct target *target,
arm_algorithm_info->core_mode);
buf_set_u32(arm->cpsr->value, 0, 5,
arm_algorithm_info->core_mode);
arm->cpsr->dirty = 1;
arm->cpsr->valid = 1;
arm->cpsr->dirty = true;
arm->cpsr->valid = true;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
@@ -1470,14 +1470,14 @@ int armv4_5_run_algorithm_inner(struct target *target,
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
i).valid = 1;
i).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
i).dirty = 1;
i).dirty = true;
}
}
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
arm->cpsr->dirty = true;
arm->core_state = core_state;
src/target/armv7a_mmu.c
-2
View File
@@ -152,8 +152,6 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
if (retval != ERROR_OK)
goto done;
*val = (*val & ~0xfff) + (va & 0xfff);
if (*val == va)
LOG_WARNING("virt = phys : MMU disable !!");
if (meminfo) {
LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured",
va, *val,
src/target/armv7m.c
+16 -16
View File
@@ -205,8 +205,8 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_cpy(buf, reg->value, reg->size);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
@@ -244,8 +244,8 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r,
buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
}
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
armv7m->arm.core_cache->reg_list[num].valid = true;
armv7m->arm.core_cache->reg_list[num].dirty = false;
return retval;
}
@@ -283,8 +283,8 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r,
goto out_error;
}
armv7m->arm.core_cache->reg_list[num].valid = 1;
armv7m->arm.core_cache->reg_list[num].dirty = 0;
armv7m->arm.core_cache->reg_list[num].valid = true;
armv7m->arm.core_cache->reg_list[num].dirty = false;
return ERROR_OK;
@@ -424,8 +424,8 @@ int armv7m_start_algorithm(struct target *target,
*/
struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
buf_set_u32(reg->value, 0, 32, 0x01000000);
reg->valid = 1;
reg->dirty = 1;
reg->valid = true;
reg->dirty = true;
}
if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
@@ -440,8 +440,8 @@ int armv7m_start_algorithm(struct target *target,
LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
0, 1, armv7m_algorithm_info->core_mode);
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
}
/* save previous core mode */
@@ -535,8 +535,8 @@ int armv7m_wait_algorithm(struct target *target,
armv7m_algorithm_info->context[i]);
buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
0, 32, armv7m_algorithm_info->context[i]);
armv7m->arm.core_cache->reg_list[i].valid = 1;
armv7m->arm.core_cache->reg_list[i].dirty = 1;
armv7m->arm.core_cache->reg_list[i].valid = true;
armv7m->arm.core_cache->reg_list[i].dirty = true;
}
}
@@ -545,8 +545,8 @@ int armv7m_wait_algorithm(struct target *target,
LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
0, 1, armv7m_algorithm_info->core_mode);
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
}
armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
@@ -619,8 +619,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
if (storage_size < 4)
storage_size = 4;
reg_list[i].value = calloc(1, storage_size);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].type = &armv7m_reg_type;
reg_list[i].arch_info = &arch_info[i];
src/target/armv7m_trace.c
+2 -1
View File
@@ -116,7 +116,8 @@ int armv7m_trace_tpiu_config(struct target *target)
return retval;
if (trace_config->config_type == TRACE_CONFIG_TYPE_INTERNAL)
target_register_timer_callback(armv7m_poll_trace, 1, 1, target);
target_register_timer_callback(armv7m_poll_trace, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
target_call_event_callbacks(target, TARGET_EVENT_TRACE_CONFIG);
src/target/armv8.c
+81 -8
View File
@@ -678,8 +678,8 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
*/
if (arm->cpsr) {
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
arm->cpsr->valid = 1;
arm->cpsr->dirty = 0;
arm->cpsr->valid = true;
arm->cpsr->dirty = false;
}
/* Older ARMs won't have the J bit */
@@ -1013,6 +1013,72 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
return retval;
}
COMMAND_HANDLER(armv8_handle_exception_catch_command)
{
struct target *target = get_current_target(CMD_CTX);
struct armv8_common *armv8 = target_to_armv8(target);
uint32_t edeccr = 0;
unsigned int argp = 0;
int retval;
static const Jim_Nvp nvp_ecatch_modes[] = {
{ .name = "off", .value = 0 },
{ .name = "nsec_el1", .value = (1 << 5) },
{ .name = "nsec_el2", .value = (2 << 5) },
{ .name = "nsec_el12", .value = (3 << 5) },
{ .name = "sec_el1", .value = (1 << 1) },
{ .name = "sec_el3", .value = (4 << 1) },
{ .name = "sec_el13", .value = (5 << 1) },
{ .name = NULL, .value = -1 },
};
const Jim_Nvp *n;
if (CMD_ARGC == 0) {
const char *sec = NULL, *nsec = NULL;
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_ECCR, &edeccr);
if (retval != ERROR_OK)
return retval;
n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
if (n->name != NULL)
sec = n->name;
n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
if (n->name != NULL)
nsec = n->name;
if (sec == NULL || nsec == NULL) {
LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
return ERROR_FAIL;
}
command_print(CMD_CTX, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
return ERROR_OK;
}
while (CMD_ARGC > argp) {
n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
if (n->name == NULL) {
LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
return ERROR_FAIL;
}
LOG_DEBUG("found: %s", n->name);
edeccr |= n->value;
argp++;
}
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_ECCR, edeccr);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
struct armv8_cache_common *armv8_cache)
{
@@ -1452,17 +1518,17 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
armv8_set_cpsr(arm, (uint32_t)value);
else {
buf_set_u64(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->valid = true;
}
} else if (reg->size <= 128) {
uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64);
buf_set_u64(reg->value, 0, 64, value);
buf_set_u64(reg->value + 8, 0, reg->size - 64, hvalue);
reg->valid = 1;
reg->valid = true;
}
reg->dirty = 1;
reg->dirty = true;
return ERROR_OK;
}
@@ -1519,11 +1585,11 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
uint64_t value64 = buf_get_u64(buf, 0, 64);
buf_set_u64(reg->value, 0, 64, value64);
}
reg->valid = 1;
reg64->valid = 1;
reg->valid = true;
reg64->valid = true;
}
reg64->dirty = 1;
reg64->dirty = true;
return ERROR_OK;
}
@@ -1675,6 +1741,13 @@ void armv8_free_reg_cache(struct target *target)
}
const struct command_registration armv8_command_handlers[] = {
{
.name = "catch_exc",
.handler = armv8_handle_exception_catch_command,
.mode = COMMAND_EXEC,
.help = "configure exception catch",
.usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]",
},
COMMAND_REGISTRATION_DONE
};
src/target/armv8.h
+1
View File
@@ -261,6 +261,7 @@ static inline bool is_armv8(struct armv8_common *armv8)
#define CPUV8_DBG_WFAR1 0x34
#define CPUV8_DBG_DSCR 0x088
#define CPUV8_DBG_DRCR 0x090
#define CPUV8_DBG_ECCR 0x098
#define CPUV8_DBG_PRCR 0x310
#define CPUV8_DBG_PRSR 0x314
src/target/armv8_dpm.c
+3 -1
View File
@@ -1381,13 +1381,15 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
target->debug_reason = DBG_REASON_EXC_CATCH;
break;
default:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
src/target/avr32_ap7k.c
+8 -8
View File
@@ -110,8 +110,8 @@ static int avr32_read_core_reg(struct target *target, int num)
reg_value = ap7k->core_regs[num];
buf_set_u32(ap7k->core_cache->reg_list[num].value, 0, 32, reg_value);
ap7k->core_cache->reg_list[num].valid = 1;
ap7k->core_cache->reg_list[num].dirty = 0;
ap7k->core_cache->reg_list[num].valid = true;
ap7k->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -129,8 +129,8 @@ static int avr32_write_core_reg(struct target *target, int num)
reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
ap7k->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
ap7k->core_cache->reg_list[num].valid = 1;
ap7k->core_cache->reg_list[num].dirty = 0;
ap7k->core_cache->reg_list[num].valid = true;
ap7k->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -159,8 +159,8 @@ static int avr32_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
@@ -196,8 +196,8 @@ static struct reg_cache *avr32_build_reg_cache(struct target *target)
reg_list[i].name = avr32_core_reg_list[i];
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].type = &avr32_reg_type;
reg_list[i].arch_info = &arch_info[i];
}
src/target/breakpoints.c
+14 -12
View File
@@ -41,7 +41,7 @@ static const char * const watchpoint_rw_strings[] = {
/* monotonic counter/id-number for breakpoints and watch points */
static int bpwp_unique_id;
int breakpoint_add_internal(struct target *target,
static int breakpoint_add_internal(struct target *target,
target_addr_t address,
uint32_t length,
enum breakpoint_type type)
@@ -60,9 +60,9 @@ int breakpoint_add_internal(struct target *target,
* breakpoint" ... check all the parameters before
* succeeding.
*/
LOG_DEBUG("Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
LOG_ERROR("Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
address, breakpoint->unique_id);
return ERROR_OK;
return ERROR_TARGET_DUPLICATE_BREAKPOINT;
}
breakpoint_p = &breakpoint->next;
breakpoint = breakpoint->next;
@@ -108,7 +108,7 @@ fail:
return ERROR_OK;
}
int context_breakpoint_add_internal(struct target *target,
static int context_breakpoint_add_internal(struct target *target,
uint32_t asid,
uint32_t length,
enum breakpoint_type type)
@@ -126,9 +126,9 @@ int context_breakpoint_add_internal(struct target *target,
* breakpoint" ... check all the parameters before
* succeeding.
*/
LOG_DEBUG("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")",
LOG_ERROR("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")",
asid, breakpoint->unique_id);
return -1;
return ERROR_TARGET_DUPLICATE_BREAKPOINT;
}
breakpoint_p = &breakpoint->next;
breakpoint = breakpoint->next;
@@ -160,7 +160,7 @@ int context_breakpoint_add_internal(struct target *target,
return ERROR_OK;
}
int hybrid_breakpoint_add_internal(struct target *target,
static int hybrid_breakpoint_add_internal(struct target *target,
target_addr_t address,
uint32_t asid,
uint32_t length,
@@ -178,13 +178,13 @@ int hybrid_breakpoint_add_internal(struct target *target,
* breakpoint" ... check all the parameters before
* succeeding.
*/
LOG_DEBUG("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")",
LOG_ERROR("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")",
asid, breakpoint->unique_id);
return -1;
return ERROR_TARGET_DUPLICATE_BREAKPOINT;
} else if ((breakpoint->address == address) && (breakpoint->asid == 0)) {
LOG_DEBUG("Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
LOG_ERROR("Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")",
address, breakpoint->unique_id);
return -1;
return ERROR_TARGET_DUPLICATE_BREAKPOINT;
}
breakpoint_p = &breakpoint->next;
@@ -243,6 +243,7 @@ int breakpoint_add(struct target *target,
} else
return breakpoint_add_internal(target, address, length, type);
}
int context_breakpoint_add(struct target *target,
uint32_t asid,
uint32_t length,
@@ -264,6 +265,7 @@ int context_breakpoint_add(struct target *target,
} else
return context_breakpoint_add_internal(target, asid, length, type);
}
int hybrid_breakpoint_add(struct target *target,
target_addr_t address,
uint32_t asid,
@@ -312,7 +314,7 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint
free(breakpoint);
}
int breakpoint_remove_internal(struct target *target, target_addr_t address)
static int breakpoint_remove_internal(struct target *target, target_addr_t address)
{
struct breakpoint *breakpoint = target->breakpoints;
src/target/cortex_a.c
+26 -91
View File
@@ -56,11 +56,9 @@
#include "arm_opcodes.h"
#include "arm_semihosting.h"
#include "transport/transport.h"
#include "smp.h"
#include <helper/time_support.h>
#define foreach_smp_target(pos, head) \
for (pos = head; (pos != NULL); pos = pos->next)
static int cortex_a_poll(struct target *target);
static int cortex_a_debug_entry(struct target *target);
static int cortex_a_restore_context(struct target *target, bool bpwp);
@@ -806,15 +804,15 @@ static int cortex_a_internal_restore(struct target *target, int current,
* C_MASKINTS in parallel with disabled interrupts can cause
* local faults to not be taken. */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = true;
armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true;
/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0,
32) | (1 << 24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true;
}
#endif
@@ -848,8 +846,8 @@ static int cortex_a_internal_restore(struct target *target, int current,
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
arm->pc->dirty = 1;
arm->pc->valid = 1;
arm->pc->dirty = true;
arm->pc->valid = true;
/* restore dpm_mode at system halt */
arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
@@ -2833,15 +2831,15 @@ static int cortex_a_init_arch_info(struct target *target,
/* REVISIT v7a setup should be in a v7a-specific routine */
armv7a_init_arch_info(target, armv7a);
target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target);
target_register_timer_callback(cortex_a_handle_target_request, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
struct cortex_a_common *cortex_a;
struct adiv5_private_config *pc;
if (target->private_config == NULL)
@@ -2849,8 +2847,13 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
pc = (struct adiv5_private_config *)target->private_config;
cortex_a = calloc(1, sizeof(struct cortex_a_common));
if (cortex_a == NULL) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
cortex_a->armv7a_common.is_armv7r = false;
cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3;
return cortex_a_init_arch_info(target, cortex_a, pc->dap);
@@ -2858,14 +2861,19 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp)
static int cortex_r4_target_create(struct target *target, Jim_Interp *interp)
{
struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common));
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
struct cortex_a_common *cortex_a;
struct adiv5_private_config *pc;
pc = (struct adiv5_private_config *)target->private_config;
if (adiv5_verify_config(pc) != ERROR_OK)
return ERROR_FAIL;
cortex_a = calloc(1, sizeof(struct cortex_a_common));
if (cortex_a == NULL) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
cortex_a->common_magic = CORTEX_A_COMMON_MAGIC;
cortex_a->armv7a_common.is_armv7r = true;
return cortex_a_init_arch_info(target, cortex_a, pc->dap);
@@ -2959,63 +2967,6 @@ COMMAND_HANDLER(cortex_a_handle_dbginit_command)
return cortex_a_init_debug_access(target);
}
COMMAND_HANDLER(cortex_a_handle_smp_off_command)
{
struct target *target = get_current_target(CMD_CTX);
/* check target is an smp target */
struct target_list *head;
struct target *curr;
head = target->head;
target->smp = 0;
if (head != (struct target_list *)NULL) {
while (head != (struct target_list *)NULL) {
curr = head->target;
curr->smp = 0;
head = head->next;
}
/* fixes the target display to the debugger */
target->gdb_service->target = target;
}
return ERROR_OK;
}
COMMAND_HANDLER(cortex_a_handle_smp_on_command)
{
struct target *target = get_current_target(CMD_CTX);
struct target_list *head;
struct target *curr;
head = target->head;
if (head != (struct target_list *)NULL) {
target->smp = 1;
while (head != (struct target_list *)NULL) {
curr = head->target;
curr->smp = 1;
head = head->next;
}
}
return ERROR_OK;
}
COMMAND_HANDLER(cortex_a_handle_smp_gdb_command)
{
struct target *target = get_current_target(CMD_CTX);
int retval = ERROR_OK;
struct target_list *head;
head = target->head;
if (head != (struct target_list *)NULL) {
if (CMD_ARGC == 1) {
int coreid = 0;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
if (ERROR_OK != retval)
return retval;
target->gdb_service->core[1] = coreid;
}
command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
, target->gdb_service->core[1]);
}
return ERROR_OK;
}
COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
{
@@ -3086,25 +3037,6 @@ static const struct command_registration cortex_a_exec_command_handlers[] = {
.help = "Initialize core debug",
.usage = "",
},
{ .name = "smp_off",
.handler = cortex_a_handle_smp_off_command,
.mode = COMMAND_EXEC,
.help = "Stop smp handling",
.usage = "",},
{
.name = "smp_on",
.handler = cortex_a_handle_smp_on_command,
.mode = COMMAND_EXEC,
.help = "Restart smp handling",
.usage = "",
},
{
.name = "smp_gdb",
.handler = cortex_a_handle_smp_gdb_command,
.mode = COMMAND_EXEC,
.help = "display/fix current core played to gdb",
.usage = "",
},
{
.name = "maskisr",
.handler = handle_cortex_a_mask_interrupts_command,
@@ -3123,6 +3055,9 @@ static const struct command_registration cortex_a_exec_command_handlers[] = {
{
.chain = armv7a_mmu_command_handlers,
},
{
.chain = smp_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
src/target/cortex_m.c
+16 -43
View File
@@ -265,7 +265,7 @@ static int cortex_m_endreset_event(struct target *target)
return retval;
}
cortex_m->fpb_enabled = 1;
cortex_m->fpb_enabled = true;
/* Restore FPB registers */
for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
@@ -1164,7 +1164,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
fp_num++;
if (fp_num >= cortex_m->fp_num_code) {
LOG_ERROR("Can not find free FPB Comparator!");
return ERROR_FAIL;
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
breakpoint->set = fp_num + 1;
fpcr_value = breakpoint->address | 1;
@@ -1180,7 +1180,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
return ERROR_FAIL;
}
comparator_list[fp_num].used = 1;
comparator_list[fp_num].used = true;
comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
@@ -1195,7 +1195,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
return retval;
}
cortex_m->fpb_enabled = 1;
cortex_m->fpb_enabled = true;
}
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
@@ -1254,23 +1254,17 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
LOG_DEBUG("Invalid FP Comparator number in breakpoint");
return ERROR_OK;
}
comparator_list[fp_num].used = 0;
comparator_list[fp_num].used = false;
comparator_list[fp_num].fpcr_value = 0;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
} else {
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4) {
retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE,
breakpoint->length, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
} else {
retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
breakpoint->orig_instr);
if (retval != ERROR_OK)
return retval;
}
if (retval != ERROR_OK)
return retval;
}
breakpoint->set = false;
@@ -1279,13 +1273,6 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length == 3) {
LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
breakpoint->length = 2;
@@ -1296,29 +1283,15 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->type == BKPT_HARD)
cortex_m->fp_code_available--;
return cortex_m_set_breakpoint(target, breakpoint);
}
int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
if (!breakpoint->set)
return ERROR_OK;
/* REVISIT why check? FPB can be updated with core running ... */
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (breakpoint->set)
cortex_m_unset_breakpoint(target, breakpoint);
if (breakpoint->type == BKPT_HARD)
cortex_m->fp_code_available++;
return ERROR_OK;
return cortex_m_unset_breakpoint(target, breakpoint);
}
int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
@@ -1351,7 +1324,7 @@ int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint
LOG_ERROR("Can not find free DWT Comparator");
return ERROR_FAIL;
}
comparator->used = 1;
comparator->used = true;
watchpoint->set = dwt_num + 1;
comparator->comp = watchpoint->address;
@@ -1408,7 +1381,7 @@ int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoi
}
comparator = cortex_m->dwt_comparator_list + dwt_num;
comparator->used = 0;
comparator->used = false;
comparator->function = 0;
target_write_u32(target, comparator->dwt_comparator_address + 8,
comparator->function);
@@ -2127,7 +2100,6 @@ int cortex_m_examine(struct target *target)
/* bits [14:12] and [7:4] */
cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m->fp_code_available = cortex_m->fp_num_code;
/* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
Revision is zero base, fp_rev == 1 means Rev.2 ! */
cortex_m->fp_rev = (fpcr >> 28) & 0xf;
@@ -2269,7 +2241,8 @@ static int cortex_m_init_arch_info(struct target *target,
armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
target_register_timer_callback(cortex_m_handle_target_request, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
src/target/cortex_m.h
+3 -4
View File
@@ -136,14 +136,14 @@
#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
struct cortex_m_fp_comparator {
int used;
bool used;
int type;
uint32_t fpcr_value;
uint32_t fpcr_address;
};
struct cortex_m_dwt_comparator {
int used;
bool used;
uint32_t comp;
uint32_t mask;
uint32_t function;
@@ -172,9 +172,8 @@ struct cortex_m_common {
/* Flash Patch and Breakpoint (FPB) */
int fp_num_lit;
int fp_num_code;
int fp_code_available;
int fp_rev;
int fpb_enabled;
bool fpb_enabled;
struct cortex_m_fp_comparator *fp_comparator_list;
/* Data Watchpoint and Trace (DWT) */
src/target/dsp563xx.c
+23 -23
View File
@@ -384,8 +384,8 @@ static int dsp563xx_read_core_reg(struct target *target, int num)
reg_value = dsp563xx->core_regs[num];
buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value);
dsp563xx->core_cache->reg_list[num].valid = 1;
dsp563xx->core_cache->reg_list[num].dirty = 0;
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -400,8 +400,8 @@ static int dsp563xx_write_core_reg(struct target *target, int num)
reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32);
dsp563xx->core_regs[num] = reg_value;
dsp563xx->core_cache->reg_list[num].valid = 1;
dsp563xx->core_cache->reg_list[num].dirty = 0;
dsp563xx->core_cache->reg_list[num].valid = true;
dsp563xx->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -432,8 +432,8 @@ static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, reg->size, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
@@ -473,8 +473,8 @@ static void dsp563xx_build_reg_cache(struct target *target)
reg_list[i].name = dsp563xx_regs[i].name;
reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].type = &dsp563xx_reg_type;
reg_list[i].arch_info = &arch_info[i];
}
@@ -508,7 +508,7 @@ static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask,
if (err != ERROR_OK)
return err;
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
@@ -534,7 +534,7 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask
return err;
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
return ERROR_OK;
}
@@ -745,7 +745,7 @@ static int dsp563xx_read_register(struct target *target, int num, int force)
struct dsp563xx_core_reg *arch_info;
if (force)
dsp563xx->core_cache->reg_list[num].valid = 0;
dsp563xx->core_cache->reg_list[num].valid = false;
if (!dsp563xx->core_cache->reg_list[num].valid) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
@@ -795,7 +795,7 @@ static int dsp563xx_write_register(struct target *target, int num, int force)
struct dsp563xx_core_reg *arch_info;
if (force)
dsp563xx->core_cache->reg_list[num].dirty = 1;
dsp563xx->core_cache->reg_list[num].dirty = true;
if (dsp563xx->core_cache->reg_list[num].dirty) {
arch_info = dsp563xx->core_cache->reg_list[num].arch_info;
@@ -884,8 +884,8 @@ static void dsp563xx_invalidate_x_context(struct target *target,
if ((arch_info->instr_mask >= addr_start) &&
(arch_info->instr_mask <= addr_end)) {
dsp563xx->core_cache->reg_list[i].valid = 0;
dsp563xx->core_cache->reg_list[i].dirty = 0;
dsp563xx->core_cache->reg_list[i].valid = false;
dsp563xx->core_cache->reg_list[i].dirty = false;
}
}
}
@@ -985,7 +985,7 @@ static int dsp563xx_debug_init(struct target *target)
err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr);
if (err != ERROR_OK)
return err;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true;
}
err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0);
@@ -1007,7 +1007,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info;
@@ -1015,7 +1015,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info;
@@ -1023,7 +1023,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true;
if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) {
arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info;
@@ -1031,7 +1031,7 @@ static int dsp563xx_debug_init(struct target *target)
if (err != ERROR_OK)
return err;
}
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true;
err = dsp563xx_save_context(target);
if (err != ERROR_OK)
@@ -1552,9 +1552,9 @@ static int dsp563xx_read_memory_core(struct target *target,
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
@@ -1734,9 +1734,9 @@ static int dsp563xx_write_memory_core(struct target *target,
dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1);
/* r0 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true;
/* r1 is no longer valid on target */
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1;
dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true;
x = count;
b = buffer;
src/target/embeddedice.c
+4 -4
View File
@@ -205,8 +205,8 @@ struct reg_cache *embeddedice_build_reg_cache(struct target *target,
for (i = 0; i < num_regs; i++) {
reg_list[i].name = eice_regs[i].name;
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].type = &eice_reg_type;
@@ -470,8 +470,8 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
embeddedice_write_reg(reg, value);
buf_set_u32(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->dirty = 0;
reg->valid = true;
reg->dirty = false;
}
src/target/etb.c
+4 -4
View File
@@ -143,8 +143,8 @@ struct reg_cache *etb_build_reg_cache(struct etb *etb)
for (i = 0; i < num_regs; i++) {
reg_list[i].name = etb_reg_list[i];
reg_list[i].size = 32;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].type = &etb_reg_type;
@@ -272,8 +272,8 @@ static int etb_set_reg(struct reg *reg, uint32_t value)
}
buf_set_u32(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->dirty = 0;
reg->valid = true;
reg->dirty = false;
return ERROR_OK;
}
src/target/feroceon.c
+6 -6
View File
@@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target,
/* set up target address in r0 */
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
arm->core_cache->reg_list[0].valid = 1;
arm->core_cache->reg_list[0].dirty = 1;
arm->core_cache->reg_list[0].valid = true;
arm->core_cache->reg_list[0].dirty = true;
arm->core_state = ARM_STATE_ARM;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
@@ -575,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target,
/* restore target state */
for (i = 0; i <= 5; i++) {
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
arm->core_cache->reg_list[i].valid = 1;
arm->core_cache->reg_list[i].dirty = 1;
arm->core_cache->reg_list[i].valid = true;
arm->core_cache->reg_list[i].dirty = true;
}
buf_set_u32(arm->pc->value, 0, 32, save[i]);
arm->pc->valid = 1;
arm->pc->dirty = 1;
arm->pc->valid = true;
arm->pc->dirty = true;
arm->core_state = core_state;
return retval;
src/target/hla_target.c
+2 -1
View File
@@ -346,7 +346,8 @@ static int adapter_init_arch_info(struct target *target,
armv7m->examine_debug_reason = adapter_examine_debug_reason;
armv7m->stlink = true;
target_register_timer_callback(hl_handle_target_request, 1, 1, target);
target_register_timer_callback(hl_handle_target_request, 1,
TARGET_TIMER_TYPE_PERIODIC, target);
return ERROR_OK;
}
src/target/lakemont.c
+12 -12
View File
@@ -322,8 +322,8 @@ static int restore_context(struct target *t)
}
for (i = 0; i < (x86_32->cache->num_regs); i++) {
x86_32->cache->reg_list[i].dirty = 0;
x86_32->cache->reg_list[i].valid = 0;
x86_32->cache->reg_list[i].dirty = false;
x86_32->cache->reg_list[i].valid = false;
}
return err;
}
@@ -357,8 +357,8 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
@@ -405,8 +405,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t)
reg_list[i].name = regs[i].name;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].dirty = false;
reg_list[i].valid = false;
reg_list[i].type = &lakemont_reg_type;
reg_list[i].arch_info = &arch_info[i];
@@ -667,8 +667,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
*regval = buf_get_u32(scan.out, 0, 32);
if (cache) {
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
x86_32->cache->reg_list[reg].valid = 1;
x86_32->cache->reg_list[reg].dirty = 0;
x86_32->cache->reg_list[reg].valid = true;
x86_32->cache->reg_list[reg].dirty = false;
}
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
@@ -709,8 +709,8 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
/* we are writing from the cache so ensure we reset flags */
if (cache) {
x86_32->cache->reg_list[reg].dirty = 0;
x86_32->cache->reg_list[reg].valid = 0;
x86_32->cache->reg_list[reg].dirty = false;
x86_32->cache->reg_list[reg].valid = false;
}
return ERROR_OK;
}
@@ -947,8 +947,8 @@ int lakemont_poll(struct target *t)
* breakpoint instruction. This needs to be corrected.
*/
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
x86_32->cache->reg_list[EIP].dirty = 1;
x86_32->cache->reg_list[EIP].valid = 1;
x86_32->cache->reg_list[EIP].dirty = true;
x86_32->cache->reg_list[EIP].valid = true;
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
} else {
/* it's not a hardware breakpoint (checked already in DR6 state)
src/target/mem_ap.c
+7 -1
View File
@@ -31,7 +31,7 @@ struct mem_ap {
static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
{
struct mem_ap *mem_ap = calloc(1, sizeof(struct mem_ap));
struct mem_ap *mem_ap;
struct adiv5_private_config *pc;
pc = (struct adiv5_private_config *)target->private_config;
@@ -43,6 +43,12 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
mem_ap = calloc(1, sizeof(struct mem_ap));
if (mem_ap == NULL) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
mem_ap->ap_num = pc->ap_num;
mem_ap->arm.common_magic = ARM_COMMON_MAGIC;
mem_ap->arm.dap = pc->dap;
src/target/mips32.c
+11 -11
View File
@@ -190,8 +190,8 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
reg->valid = 1;
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
@@ -208,8 +208,8 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
reg_value = mips32->core_regs[num];
buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
mips32->core_cache->reg_list[num].valid = 1;
mips32->core_cache->reg_list[num].dirty = 0;
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -227,8 +227,8 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
mips32->core_cache->reg_list[num].valid = 1;
mips32->core_cache->reg_list[num].dirty = 0;
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -336,12 +336,12 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
reg_list[i].value = mips32_gdb_dummy_fp_value;
reg_list[i].valid = 1;
reg_list[i].valid = true;
reg_list[i].arch_info = NULL;
register_init_dummy(&reg_list[i]);
} else {
reg_list[i].value = calloc(1, 4);
reg_list[i].valid = 0;
reg_list[i].valid = false;
reg_list[i].type = &mips32_reg_type;
reg_list[i].arch_info = &arch_info[i];
@@ -352,7 +352,7 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
LOG_ERROR("unable to allocate reg type list");
}
reg_list[i].dirty = 0;
reg_list[i].dirty = false;
reg_list[i].group = mips32_regs[i].group;
reg_list[i].number = i;
@@ -532,8 +532,8 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
mips32->core_cache->reg_list[i].name, context[i]);
buf_set_u32(mips32->core_cache->reg_list[i].value,
0, 32, context[i]);
mips32->core_cache->reg_list[i].valid = 1;
mips32->core_cache->reg_list[i].dirty = 1;
mips32->core_cache->reg_list[i].valid = true;
mips32->core_cache->reg_list[i].dirty = true;
}
}

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