auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' into from_upstream

Browse Source 
Conflicts:
	src/flash/nor/at91sam4.c
	src/flash/nor/at91sam4l.c
	src/flash/nor/at91samd.c
	src/flash/nor/ath79.c
	src/flash/nor/atsame5.c
	src/flash/nor/cfi.c
	src/flash/nor/core.c
	src/flash/nor/fespi.c
	src/flash/nor/kinetis.c
	src/flash/nor/kinetis_ke.c
	src/flash/nor/lpc2000.c
	src/flash/nor/niietcm4.c
	src/flash/nor/nrf5.c
	src/flash/nor/numicro.c
	src/flash/nor/pic32mx.c
	src/flash/nor/stm32h7x.c
	src/flash/nor/stm32lx.c
	src/flash/nor/stmsmi.c
	src/flash/nor/tcl.c
	src/flash/nor/tms470.c
	src/flash/nor/virtual.c
	src/flash/nor/xmc4xxx.c
	src/rtos/hwthread.c
	src/rtos/rtos.c
	src/server/gdb_server.c
	src/target/riscv/riscv-011.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h

Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
This commit is contained in:
Tim Newsome
2019-04-03 12:38:27 -07:00
parent c089e6ae9a 11a2bfc2bc
commit 79f9672615
120 changed files with 1233 additions and 936 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/flash/nor/aduc702x.c
+1 -1
View File
@@ -378,7 +378,7 @@ static int aduc702x_check_flash_completion(struct target *target, unsigned int t
return ERROR_OK;
}
struct flash_driver aduc702x_flash = {
const struct flash_driver aduc702x_flash = {
.name = "aduc702x",
.flash_bank_command = aduc702x_flash_bank_command,
.erase = aduc702x_erase,
src/flash/nor/aducm360.c
+1 -1
View File
@@ -554,7 +554,7 @@ static int aducm360_check_flash_completion(struct target *target, unsigned int t
}
/* ----------------------------------------------------------------------- */
struct flash_driver aducm360_flash = {
const struct flash_driver aducm360_flash = {
.name = "aducm360",
.flash_bank_command = aducm360_flash_bank_command,
.erase = aducm360_erase,
src/flash/nor/ambiqmicro.c
+1 -1
View File
@@ -888,7 +888,7 @@ static const struct command_registration ambiqmicro_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver ambiqmicro_flash = {
const struct flash_driver ambiqmicro_flash = {
.name = "ambiqmicro",
.commands = ambiqmicro_command_handlers,
.flash_bank_command = ambiqmicro_flash_bank_command,
src/flash/nor/at91sam3.c
+2 -2
View File
@@ -109,7 +109,7 @@
#define offset_EFC_FSR 8
#define offset_EFC_FRR 12
extern struct flash_driver at91sam3_flash;
extern const struct flash_driver at91sam3_flash;
static float _tomhz(uint32_t freq_hz)
{
@@ -3753,7 +3753,7 @@ static const struct command_registration at91sam3_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam3_flash = {
const struct flash_driver at91sam3_flash = {
.name = "at91sam3",
.commands = at91sam3_command_handlers,
.flash_bank_command = sam3_flash_bank_command,
src/flash/nor/at91sam4.c
+5 -5
View File
@@ -103,7 +103,7 @@
#define offset_EFC_FSR 8
#define offset_EFC_FRR 12
extern struct flash_driver at91sam4_flash;
extern const struct flash_driver at91sam4_flash;
static float _tomhz(uint32_t freq_hz)
{
@@ -2598,7 +2598,7 @@ static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
}
snprintf(buf, buf_size,
"%s bank %d: %d kB at 0x%08" TARGET_PRIxADDR,
"%s bank %d: %d kB at " TARGET_ADDR_FMT,
pPrivate->pChip->details.name,
pPrivate->bank_number,
k,
@@ -2642,8 +2642,8 @@ static int sam4_probe(struct flash_bank *bank)
for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
bank->size = pPrivate->pChip->details.bank[x].size_bytes;
LOG_DEBUG("SAM4 Set flash bank to %" TARGET_PRIxADDR " - %"
TARGET_PRIxADDR ", idx %d", bank->base,
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
TARGET_ADDR_FMT ", idx %d", bank->base,
bank->base + bank->size, x);
break;
}
@@ -3234,7 +3234,7 @@ static const struct command_registration at91sam4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam4_flash = {
const struct flash_driver at91sam4_flash = {
.name = "at91sam4",
.commands = at91sam4_command_handlers,
.flash_bank_command = sam4_flash_bank_command,
src/flash/nor/at91sam4l.c
+2 -2
View File
@@ -203,7 +203,7 @@ static int sam4l_flash_command(struct target *target, uint8_t cmd, int page)
FLASH_BANK_COMMAND_HANDLER(sam4l_flash_bank_command)
{
if (bank->base != SAM4L_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR
LOG_ERROR("Address " TARGET_ADDR_FMT
" invalid bank address (try 0x%08" PRIx32
"[at91sam4l series] )",
bank->base, SAM4L_FLASH);
@@ -684,7 +684,7 @@ static const struct command_registration at91sam4l_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam4l_flash = {
const struct flash_driver at91sam4l_flash = {
.name = "at91sam4l",
.commands = at91sam4l_command_handlers,
.flash_bank_command = sam4l_flash_bank_command,
src/flash/nor/at91sam7.c
+1 -1
View File
@@ -1140,7 +1140,7 @@ static const struct command_registration at91sam7_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91sam7_flash = {
const struct flash_driver at91sam7_flash = {
.name = "at91sam7",
.usage = "gpnvm <bit> <set | clear>",
.commands = at91sam7_command_handlers,
src/flash/nor/at91samd.c
+2 -2
View File
@@ -906,7 +906,7 @@ free_pb:
FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR
LOG_ERROR("Address " TARGET_ADDR_FMT
" invalid bank address (try 0x%08" PRIx32
"[at91samd series] )",
bank->base, SAMD_FLASH);
@@ -1287,7 +1287,7 @@ static const struct command_registration at91samd_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver at91samd_flash = {
const struct flash_driver at91samd_flash = {
.name = "at91samd",
.commands = at91samd_command_handlers,
.flash_bank_command = samd_flash_bank_command,
src/flash/nor/ath79.c
+2 -2
View File
@@ -794,7 +794,7 @@ static int ath79_probe(struct flash_bank *bank)
ath79_info->io_base = target_device->io_base;
LOG_DEBUG("Found device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Found device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
retval = read_flash_id(bank, &id);
@@ -895,7 +895,7 @@ static int get_ath79_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver ath79_flash = {
const struct flash_driver ath79_flash = {
.name = "ath79",
.flash_bank_command = ath79_flash_bank_command,
.erase = ath79_erase,
src/flash/nor/atsame5.c
+2 -2
View File
@@ -730,7 +730,7 @@ free_pb:
FLASH_BANK_COMMAND_HANDLER(same5_flash_bank_command)
{
if (bank->base != SAMD_FLASH) {
LOG_ERROR("Address 0x%08" TARGET_PRIxADDR " invalid bank address (try "
LOG_ERROR("Address " TARGET_ADDR_FMT " invalid bank address (try "
"0x%08" PRIx32 "[same5] )", bank->base, SAMD_FLASH);
return ERROR_FAIL;
}
@@ -938,7 +938,7 @@ static const struct command_registration same5_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver atsame5_flash = {
const struct flash_driver atsame5_flash = {
.name = "atsame5",
.commands = same5_command_handlers,
.flash_bank_command = same5_flash_bank_command,
src/flash/nor/atsamv.c
+2 -2
View File
@@ -94,7 +94,7 @@
#define SAMV_PAGE_SIZE 512
#define SAMV_FLASH_BASE 0x00400000
extern struct flash_driver atsamv_flash;
extern const struct flash_driver atsamv_flash;
struct samv_flash_bank {
int probed;
@@ -726,7 +726,7 @@ static const struct command_registration atsamv_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver atsamv_flash = {
const struct flash_driver atsamv_flash = {
.name = "atsamv",
.commands = atsamv_command_handlers,
.flash_bank_command = samv_flash_bank_command,
src/flash/nor/avrf.c
+1 -1
View File
@@ -462,7 +462,7 @@ static const struct command_registration avrf_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver avr_flash = {
const struct flash_driver avr_flash = {
.name = "avr",
.commands = avrf_command_handlers,
.flash_bank_command = avrf_flash_bank_command,
src/flash/nor/bluenrg-x.c
+4 -4
View File
@@ -404,9 +404,9 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
/* Stack pointer for program working area */
buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
LOG_DEBUG("source->address = %08" TARGET_PRIxADDR, source->address);
LOG_DEBUG("source->address+ source->size = %08" TARGET_PRIxADDR, source->address+source->size);
LOG_DEBUG("write_algorithm_sp->address = %08" TARGET_PRIxADDR, write_algorithm_sp->address);
LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
LOG_DEBUG("address = %08x", address+pre_size);
LOG_DEBUG("count = %08x", count);
@@ -539,7 +539,7 @@ static int bluenrgx_get_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver bluenrgx_flash = {
const struct flash_driver bluenrgx_flash = {
.name = "bluenrg-x",
.flash_bank_command = bluenrgx_flash_bank_command,
.erase = bluenrgx_erase,
src/flash/nor/cc26xx.c
+1 -1
View File
@@ -535,7 +535,7 @@ static int cc26xx_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver cc26xx_flash = {
const struct flash_driver cc26xx_flash = {
.name = "cc26xx",
.flash_bank_command = cc26xx_flash_bank_command,
.erase = cc26xx_erase,
src/flash/nor/cc3220sf.c
+1 -1
View File
@@ -489,7 +489,7 @@ static int cc3220sf_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver cc3220sf_flash = {
const struct flash_driver cc3220sf_flash = {
.name = "cc3220sf",
.flash_bank_command = cc3220sf_flash_bank_command,
.erase = cc3220sf_erase,
src/flash/nor/cfi.c
+12 -12
View File
@@ -889,8 +889,8 @@ static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
TARGET_PRIxADDR, i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -937,8 +937,8 @@ static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
TARGET_PRIxADDR, i, bank->base);
LOG_ERROR("couldn't erase block %i of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
@@ -2001,7 +2001,7 @@ static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write word at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
", address 0x%" PRIx32,
bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2027,7 +2027,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
/* Check for valid range */
if (address & buffermask) {
LOG_ERROR("Write address at base 0x%" TARGET_PRIxADDR ", address 0x%"
LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%"
PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2057,7 +2057,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
return retval;
LOG_ERROR(
"couldn't start buffer write operation at base 0x%" TARGET_PRIxADDR
"couldn't start buffer write operation at base " TARGET_ADDR_FMT
", address 0x%" PRIx32,
bank->base,
address);
@@ -2087,7 +2087,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word,
if (retval != ERROR_OK)
return retval;
LOG_ERROR("Buffer write at base 0x%" TARGET_PRIxADDR
LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2123,7 +2123,7 @@ static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint3
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write word at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
", address 0x%" PRIx32, bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2149,7 +2149,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word
/* Check for valid range */
if (address & buffermask) {
LOG_ERROR("Write address at base 0x%" TARGET_PRIxADDR
LOG_ERROR("Write address at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 " not aligned to 2^%d boundary",
bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
@@ -2195,7 +2195,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word
if (retval != ERROR_OK)
return retval;
LOG_ERROR("couldn't write block at base 0x%" TARGET_PRIxADDR
LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
@@ -3112,7 +3112,7 @@ static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *par
cfi_info->buf_write_timeout_typ = 0;
}
struct flash_driver cfi_flash = {
const struct flash_driver cfi_flash = {
.name = "cfi",
.flash_bank_command = cfi_flash_bank_command,
.erase = cfi_erase,
src/flash/nor/core.c
+29 -30
View File
@@ -99,7 +99,7 @@ int flash_driver_write(struct flash_bank *bank,
retval = bank->driver->write(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
"error writing to flash at address 0x%08" TARGET_PRIxADDR
"error writing to flash at address " TARGET_ADDR_FMT
" at offset 0x%8.8" PRIx32,
bank->base,
offset);
@@ -118,7 +118,7 @@ int flash_driver_read(struct flash_bank *bank,
retval = bank->driver->read(bank, buffer, offset, count);
if (retval != ERROR_OK) {
LOG_ERROR(
"error reading to flash at address 0x%08" TARGET_PRIxADDR
"error reading to flash at address " TARGET_ADDR_FMT
" at offset 0x%8.8" PRIx32,
bank->base,
offset);
@@ -270,7 +270,7 @@ int get_flash_bank_by_num(int num, struct flash_bank **bank)
/* lookup flash bank by address, bank not found is success, but
* result_bank is set to NULL. */
int get_flash_bank_by_addr(struct target *target,
uint32_t addr,
target_addr_t addr,
bool check,
struct flash_bank **result_bank)
{
@@ -296,7 +296,7 @@ int get_flash_bank_by_addr(struct target *target,
}
*result_bank = NULL;
if (check) {
LOG_ERROR("No flash at address 0x%08" PRIx32, addr);
LOG_ERROR("No flash at address " TARGET_ADDR_FMT, addr);
return ERROR_FAIL;
}
return ERROR_OK;
@@ -416,13 +416,13 @@ int default_flash_blank_check(struct flash_bank *bank)
* warning about those additions.
*/
static int flash_iterate_address_range_inner(struct target *target,
char *pad_reason, uint32_t addr, uint32_t length,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
struct flash_bank *c;
struct flash_sector *block_array;
uint32_t last_addr = addr + length; /* first address AFTER end */
target_addr_t last_addr = addr + length - 1; /* the last address of range */
int first = -1;
int last = -1;
int i;
@@ -448,7 +448,7 @@ static int flash_iterate_address_range_inner(struct target *target,
}
/* check whether it all fits in this bank */
if (addr + length - 1 > c->base + c->size - 1) {
if (last_addr > c->base + c->size - 1) {
LOG_ERROR("Flash access does not fit into bank.");
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -466,21 +466,19 @@ static int flash_iterate_address_range_inner(struct target *target,
num_blocks = c->num_sectors;
}
addr -= c->base;
last_addr -= c->base;
for (i = 0; i < num_blocks; i++) {
struct flash_sector *f = &block_array[i];
uint32_t end = f->offset + f->size;
target_addr_t sector_addr = c->base + f->offset;
target_addr_t sector_last_addr = sector_addr + f->size - 1;
/* start only on a sector boundary */
if (first < 0) {
/* scanned past the first sector? */
if (addr < f->offset)
if (addr < sector_addr)
break;
/* is this the first sector? */
if (addr == f->offset)
if (addr == sector_addr)
first = i;
/* Does this need head-padding? If so, pad and warn;
@@ -490,20 +488,20 @@ static int flash_iterate_address_range_inner(struct target *target,
* ever know if that data was in use. The warning
* should help users sort out messes later.
*/
else if (addr < end && pad_reason) {
else if (addr <= sector_last_addr && pad_reason) {
/* FIXME say how many bytes (e.g. 80 KB) */
LOG_WARNING("Adding extra %s range, "
"%#8.8x to %#8.8x",
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
pad_reason,
(unsigned) f->offset,
(unsigned) addr - 1);
sector_addr,
addr - 1);
first = i;
} else
continue;
}
/* is this (also?) the last sector? */
if (last_addr == end) {
if (last_addr == sector_last_addr) {
last = i;
break;
}
@@ -511,28 +509,28 @@ static int flash_iterate_address_range_inner(struct target *target,
/* Does this need tail-padding? If so, pad and warn;
* or else force an error.
*/
if (last_addr < end && pad_reason) {
if (last_addr < sector_last_addr && pad_reason) {
/* FIXME say how many bytes (e.g. 80 KB) */
LOG_WARNING("Adding extra %s range, "
"%#8.8x to %#8.8x",
TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT,
pad_reason,
(unsigned) last_addr,
(unsigned) end - 1);
last_addr + 1,
sector_last_addr);
last = i;
break;
}
/* MUST finish on a sector boundary */
if (last_addr <= f->offset)
if (last_addr < sector_addr)
break;
}
/* invalid start or end address? */
if (first == -1 || last == -1) {
LOG_ERROR("address range 0x%8.8x .. 0x%8.8x "
"is not sector-aligned",
(unsigned) (c->base + addr),
(unsigned) (c->base + last_addr - 1));
LOG_ERROR("address range " TARGET_ADDR_FMT " .. " TARGET_ADDR_FMT
" is not sector-aligned",
addr,
last_addr);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -547,7 +545,7 @@ static int flash_iterate_address_range_inner(struct target *target,
* multiple chips.
*/
static int flash_iterate_address_range(struct target *target,
char *pad_reason, uint32_t addr, uint32_t length,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
int (*callback)(struct flash_bank *bank, int first, int last))
{
@@ -581,7 +579,7 @@ static int flash_iterate_address_range(struct target *target,
}
int flash_erase_address_range(struct target *target,
bool pad, uint32_t addr, uint32_t length)
bool pad, target_addr_t addr, uint32_t length)
{
return flash_iterate_address_range(target, pad ? "erase" : NULL,
addr, length, false, &flash_driver_erase);
@@ -592,7 +590,8 @@ static int flash_driver_unprotect(struct flash_bank *bank, int first, int last)
return flash_driver_protect(bank, 0, first, last);
}
int flash_unlock_address_range(struct target *target, uint32_t addr, uint32_t length)
int flash_unlock_address_range(struct target *target, target_addr_t addr,
uint32_t length)
{
/* By default, pad to sector boundaries ... the real issue here
* is that our (only) caller *permanently* removes protection,
src/flash/nor/core.h
+4 -4
View File
@@ -87,7 +87,7 @@ struct flash_bank {
struct target *target; /**< Target to which this bank belongs. */
struct flash_driver *driver; /**< Driver for this bank. */
const struct flash_driver *driver; /**< Driver for this bank. */
void *driver_priv; /**< Private driver storage pointer */
int bank_number; /**< The 'bank' (or chip number) of this instance. */
@@ -149,9 +149,9 @@ int flash_register_commands(struct command_context *cmd_ctx);
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int flash_erase_address_range(struct target *target,
bool pad, uint32_t addr, uint32_t length);
bool pad, target_addr_t addr, uint32_t length);
int flash_unlock_address_range(struct target *target, uint32_t addr,
int flash_unlock_address_range(struct target *target, target_addr_t addr,
uint32_t length);
/**
@@ -263,7 +263,7 @@ struct flash_bank *get_flash_bank_by_num_noprobe(int num);
* @param check return ERROR_OK and result_bank NULL if the bank does not exist
* @returns The struct flash_bank located at @a addr, or NULL.
*/
int get_flash_bank_by_addr(struct target *target, uint32_t addr, bool check,
int get_flash_bank_by_addr(struct target *target, target_addr_t addr, bool check,
struct flash_bank **result_bank);
/**
* Allocate and fill an array of sectors or protection blocks.
src/flash/nor/driver.h
+1 -1
View File
@@ -231,6 +231,6 @@ struct flash_driver {
* @param name The name of the requested driver.
* @returns The flash_driver called @c name, or NULL if not found.
*/
struct flash_driver *flash_driver_find_by_name(const char *name);
const struct flash_driver *flash_driver_find_by_name(const char *name);
#endif /* OPENOCD_FLASH_NOR_DRIVER_H */
src/flash/nor/drivers.c
+65 -65
View File
@@ -20,75 +20,75 @@
#endif
#include "imp.h"
extern struct flash_driver aduc702x_flash;
extern struct flash_driver aducm360_flash;
extern struct flash_driver ambiqmicro_flash;
extern struct flash_driver at91sam3_flash;
extern struct flash_driver at91sam4_flash;
extern struct flash_driver at91sam4l_flash;
extern struct flash_driver at91sam7_flash;
extern struct flash_driver at91samd_flash;
extern struct flash_driver ath79_flash;
extern struct flash_driver atsame5_flash;
extern struct flash_driver atsamv_flash;
extern struct flash_driver avr_flash;
extern struct flash_driver bluenrgx_flash;
extern struct flash_driver cc3220sf_flash;
extern struct flash_driver cc26xx_flash;
extern struct flash_driver cfi_flash;
extern struct flash_driver dsp5680xx_flash;
extern struct flash_driver efm32_flash;
extern struct flash_driver em357_flash;
extern struct flash_driver esirisc_flash;
extern struct flash_driver faux_flash;
extern struct flash_driver fm3_flash;
extern struct flash_driver fm4_flash;
extern struct flash_driver fespi_flash;
extern struct flash_driver jtagspi_flash;
extern struct flash_driver kinetis_flash;
extern struct flash_driver kinetis_ke_flash;
extern struct flash_driver lpc2000_flash;
extern struct flash_driver lpc288x_flash;
extern struct flash_driver lpc2900_flash;
extern struct flash_driver lpcspifi_flash;
extern struct flash_driver max32xxx_flash;
extern struct flash_driver mdr_flash;
extern struct flash_driver mrvlqspi_flash;
extern struct flash_driver msp432_flash;
extern struct flash_driver niietcm4_flash;
extern struct flash_driver nrf5_flash;
extern struct flash_driver nrf51_flash;
extern struct flash_driver numicro_flash;
extern struct flash_driver ocl_flash;
extern struct flash_driver pic32mx_flash;
extern struct flash_driver psoc4_flash;
extern struct flash_driver psoc5lp_flash;
extern struct flash_driver psoc5lp_eeprom_flash;
extern struct flash_driver psoc5lp_nvl_flash;
extern struct flash_driver psoc6_flash;
extern struct flash_driver sim3x_flash;
extern struct flash_driver stellaris_flash;
extern struct flash_driver stm32f1x_flash;
extern struct flash_driver stm32f2x_flash;
extern struct flash_driver stm32lx_flash;
extern struct flash_driver stm32l4x_flash;
extern struct flash_driver stm32h7x_flash;
extern struct flash_driver stmsmi_flash;
extern struct flash_driver str7x_flash;
extern struct flash_driver str9x_flash;
extern struct flash_driver str9xpec_flash;
extern struct flash_driver tms470_flash;
extern struct flash_driver virtual_flash;
extern struct flash_driver w600_flash;
extern struct flash_driver xcf_flash;
extern struct flash_driver xmc1xxx_flash;
extern struct flash_driver xmc4xxx_flash;
extern const struct flash_driver aduc702x_flash;
extern const struct flash_driver aducm360_flash;
extern const struct flash_driver ambiqmicro_flash;
extern const struct flash_driver at91sam3_flash;
extern const struct flash_driver at91sam4_flash;
extern const struct flash_driver at91sam4l_flash;
extern const struct flash_driver at91sam7_flash;
extern const struct flash_driver at91samd_flash;
extern const struct flash_driver ath79_flash;
extern const struct flash_driver atsame5_flash;
extern const struct flash_driver atsamv_flash;
extern const struct flash_driver avr_flash;
extern const struct flash_driver bluenrgx_flash;
extern const struct flash_driver cc3220sf_flash;
extern const struct flash_driver cc26xx_flash;
extern const struct flash_driver cfi_flash;
extern const struct flash_driver dsp5680xx_flash;
extern const struct flash_driver efm32_flash;
extern const struct flash_driver em357_flash;
extern const struct flash_driver esirisc_flash;
extern const struct flash_driver faux_flash;
extern const struct flash_driver fm3_flash;
extern const struct flash_driver fm4_flash;
extern const struct flash_driver fespi_flash;
extern const struct flash_driver jtagspi_flash;
extern const struct flash_driver kinetis_flash;
extern const struct flash_driver kinetis_ke_flash;
extern const struct flash_driver lpc2000_flash;
extern const struct flash_driver lpc288x_flash;
extern const struct flash_driver lpc2900_flash;
extern const struct flash_driver lpcspifi_flash;
extern const struct flash_driver max32xxx_flash;
extern const struct flash_driver mdr_flash;
extern const struct flash_driver mrvlqspi_flash;
extern const struct flash_driver msp432_flash;
extern const struct flash_driver niietcm4_flash;
extern const struct flash_driver nrf5_flash;
extern const struct flash_driver nrf51_flash;
extern const struct flash_driver numicro_flash;
extern const struct flash_driver ocl_flash;
extern const struct flash_driver pic32mx_flash;
extern const struct flash_driver psoc4_flash;
extern const struct flash_driver psoc5lp_flash;
extern const struct flash_driver psoc5lp_eeprom_flash;
extern const struct flash_driver psoc5lp_nvl_flash;
extern const struct flash_driver psoc6_flash;
extern const struct flash_driver sim3x_flash;
extern const struct flash_driver stellaris_flash;
extern const struct flash_driver stm32f1x_flash;
extern const struct flash_driver stm32f2x_flash;
extern const struct flash_driver stm32lx_flash;
extern const struct flash_driver stm32l4x_flash;
extern const struct flash_driver stm32h7x_flash;
extern const struct flash_driver stmsmi_flash;
extern const struct flash_driver str7x_flash;
extern const struct flash_driver str9x_flash;
extern const struct flash_driver str9xpec_flash;
extern const struct flash_driver tms470_flash;
extern const struct flash_driver virtual_flash;
extern const struct flash_driver w600_flash;
extern const struct flash_driver xcf_flash;
extern const struct flash_driver xmc1xxx_flash;
extern const struct flash_driver xmc4xxx_flash;
/**
* The list of built-in flash drivers.
* @todo Make this dynamically extendable with loadable modules.
*/
static struct flash_driver *flash_drivers[] = {
static const struct flash_driver * const flash_drivers[] = {
&aduc702x_flash,
&aducm360_flash,
&ambiqmicro_flash,
@@ -155,7 +155,7 @@ static struct flash_driver *flash_drivers[] = {
NULL,
};
struct flash_driver *flash_driver_find_by_name(const char *name)
const struct flash_driver *flash_driver_find_by_name(const char *name)
{
for (unsigned i = 0; flash_drivers[i]; i++) {
if (strcmp(name, flash_drivers[i]->name) == 0)
src/flash/nor/dsp5680xx_flash.c
+1 -1
View File
@@ -256,7 +256,7 @@ static int dsp5680xx_flash_erase_check(struct flash_bank *bank)
return retval;
}
struct flash_driver dsp5680xx_flash = {
const struct flash_driver dsp5680xx_flash = {
.name = "dsp5680xx_flash",
.flash_bank_command = dsp5680xx_flash_bank_command,
.erase = dsp5680xx_flash_erase,
src/flash/nor/efm32.c
+1 -1
View File
@@ -1120,7 +1120,7 @@ static const struct command_registration efm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver efm32_flash = {
const struct flash_driver efm32_flash = {
.name = "efm32",
.commands = efm32x_command_handlers,
.flash_bank_command = efm32x_flash_bank_command,
src/flash/nor/em357.c
+1 -1
View File
@@ -929,7 +929,7 @@ static const struct command_registration em357_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver em357_flash = {
const struct flash_driver em357_flash = {
.name = "em357",
.commands = em357_command_handlers,
.flash_bank_command = em357_flash_bank_command,
src/flash/nor/esirisc_flash.c
+1 -1
View File
@@ -571,7 +571,7 @@ static const struct command_registration esirisc_flash_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver esirisc_flash = {
const struct flash_driver esirisc_flash = {
.name = "esirisc",
.usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
"cfg_address clock_hz wait_states",
src/flash/nor/faux.c
+1 -1
View File
@@ -113,7 +113,7 @@ static const struct command_registration faux_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver faux_flash = {
const struct flash_driver faux_flash = {
.name = "faux",
.commands = faux_command_handlers,
.flash_bank_command = faux_flash_bank_command,
src/flash/nor/fespi.c
+10 -10
View File
@@ -160,7 +160,7 @@ FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
fespi_info->ctrl_base = 0;
if (CMD_ARGC >= 7) {
COMMAND_PARSE_ADDRESS(CMD_ARGV[6], fespi_info->ctrl_base);
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = 0x%" TARGET_PRIxADDR,
LOG_DEBUG("ASSUMING FESPI device at ctrl_base = " TARGET_ADDR_FMT,
fespi_info->ctrl_base);
}
@@ -174,7 +174,7 @@ static int fespi_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_
int result = target_read_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
LOG_ERROR("fespi_read_reg() error at 0x%" TARGET_PRIxADDR,
LOG_ERROR("fespi_read_reg() error at " TARGET_ADDR_FMT,
fespi_info->ctrl_base + address);
return result;
}
@@ -188,7 +188,7 @@ static int fespi_write_reg(struct flash_bank *bank, target_addr_t address, uint3
int result = target_write_u32(target, fespi_info->ctrl_base + address, value);
if (result != ERROR_OK) {
LOG_ERROR("fespi_write_reg() error writing 0x%x to 0x%" TARGET_PRIxADDR,
LOG_ERROR("fespi_write_reg() error writing 0x%x to " TARGET_ADDR_FMT,
value, fespi_info->ctrl_base + address);
return result;
}
@@ -707,7 +707,7 @@ static int steps_execute(struct algorithm_steps *as,
data_buf);
free(data_buf);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to write data to 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
data_wa->address, retval);
goto exit;
}
@@ -716,7 +716,7 @@ static int steps_execute(struct algorithm_steps *as,
algorithm_wa->address, algorithm_wa->address + 4,
10000, NULL);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
goto exit;
}
@@ -773,7 +773,7 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
retval = target_write_buffer(target, algorithm_wa->address,
sizeof(algorithm_bin), algorithm_bin);
if (retval != ERROR_OK) {
LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
algorithm_wa->address, retval);
target_free_working_area(target, algorithm_wa);
algorithm_wa = NULL;
@@ -933,12 +933,12 @@ static int fespi_probe(struct flash_bank *bank)
fespi_info->ctrl_base = target_device->ctrl_base;
LOG_DEBUG("Valid FESPI on device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Valid FESPI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
} else {
LOG_DEBUG("Assuming FESPI as specified at address 0x%" TARGET_PRIxADDR
" with ctrl at 0x%" TARGET_PRIxADDR, fespi_info->ctrl_base,
LOG_DEBUG("Assuming FESPI as specified at address " TARGET_ADDR_FMT
" with ctrl at " TARGET_ADDR_FMT, fespi_info->ctrl_base,
bank->base);
}
@@ -1036,7 +1036,7 @@ static int get_fespi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver fespi_flash = {
const struct flash_driver fespi_flash = {
.name = "fespi",
.flash_bank_command = fespi_flash_bank_command,
.erase = fespi_erase,
src/flash/nor/fm3.c
+1 -1
View File
@@ -988,7 +988,7 @@ static const struct command_registration fm3_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver fm3_flash = {
const struct flash_driver fm3_flash = {
.name = "fm3",
.commands = fm3_command_handlers,
.flash_bank_command = fm3_flash_bank_command,
src/flash/nor/fm4.c
+2 -2
View File
@@ -272,7 +272,7 @@ static int fm4_flash_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t halfwords = MIN(halfword_count, data_workarea->size / 2);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(halfwords * 2, byte_count), data_workarea->address);
retval = target_write_buffer(target, data_workarea->address,
@@ -702,7 +702,7 @@ static const struct command_registration fm4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver fm4_flash = {
const struct flash_driver fm4_flash = {
.name = "fm4",
.commands = fm4_command_handlers,
.flash_bank_command = fm4_flash_bank_command,
src/flash/nor/jtagspi.c
+1 -1
View File
@@ -427,7 +427,7 @@ static int jtagspi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver jtagspi_flash = {
const struct flash_driver jtagspi_flash = {
.name = "jtagspi",
.flash_bank_command = jtagspi_flash_bank_command,
.erase = jtagspi_erase,
src/flash/nor/kinetis.c
+10 -10
View File
@@ -393,7 +393,7 @@ static bool fcf_fopt_configured;
static bool create_banks;
struct flash_driver kinetis_flash;
const struct flash_driver kinetis_flash;
static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count);
static int kinetis_probe_chip(struct kinetis_chip *k_chip);
@@ -1755,14 +1755,14 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer_aligned);
LOG_DEBUG("section @ %08" TARGET_PRIxADDR " aligned begin %" PRIu32
LOG_DEBUG("section @ " TARGET_ADDR_FMT " aligned begin %" PRIu32
", end %" PRIu32,
bank->base + offset, align_begin, align_end);
} else
result = target_write_memory(bank->target, k_chip->progr_accel_ram,
4, size_aligned / 4, buffer);
LOG_DEBUG("write section @ %08" TARGET_PRIxADDR " with length %" PRIu32
LOG_DEBUG("write section @ " TARGET_ADDR_FMT " with length %" PRIu32
" bytes",
bank->base + offset, size);
@@ -1778,13 +1778,13 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
LOG_ERROR("Error writing section at %08" TARGET_PRIxADDR,
LOG_ERROR("Error writing section at " TARGET_ADDR_FMT,
bank->base + offset);
break;
}
if (ftfx_fstat & 0x01) {
LOG_ERROR("Flash write error at %08" TARGET_PRIxADDR,
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
bank->base + offset);
if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
&& (k_chip->flash_support & FS_WIDTH_256BIT)) {
@@ -1824,7 +1824,7 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
}
}
LOG_DEBUG("flash write @ %08" TARGET_PRIxADDR, bank->base + offset);
LOG_DEBUG("flash write @ " TARGET_ADDR_FMT, bank->base + offset);
if (fallback == 0) {
/* program section command */
@@ -1877,13 +1877,13 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK) {
LOG_ERROR("Error writing longword at %08" TARGET_PRIxADDR,
LOG_ERROR("Error writing longword at " TARGET_ADDR_FMT,
bank->base + offset);
break;
}
if (ftfx_fstat & 0x01)
LOG_ERROR("Flash write error at %08" TARGET_PRIxADDR,
LOG_ERROR("Flash write error at " TARGET_ADDR_FMT,
bank->base + offset);
buffer += 4;
@@ -2775,7 +2775,7 @@ static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
uint32_t size_k = bank->size / 1024;
snprintf(buf, buf_size,
"%s %s: %" PRIu32 "k %s bank %s at 0x%08" TARGET_PRIxADDR,
"%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
bank->driver->name, k_chip->name,
size_k, bank_class_names[k_bank->flash_class],
bank->name, bank->base);
@@ -3143,7 +3143,7 @@ static const struct command_registration kinetis_command_handler[] = {
struct flash_driver kinetis_flash = {
const struct flash_driver kinetis_flash = {
.name = "kinetis",
.commands = kinetis_command_handler,
.flash_bank_command = kinetis_flash_bank_command,
src/flash/nor/kinetis_ke.c
+2 -2
View File
@@ -1175,7 +1175,7 @@ static int kinetis_ke_auto_probe(struct flash_bank *bank)
static int kinetis_ke_info(struct flash_bank *bank, char *buf, int buf_size)
{
(void) snprintf(buf, buf_size,
"%s driver for flash bank %s at 0x%8.8" TARGET_PRIxADDR,
"%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, bank->name, bank->base);
return ERROR_OK;
@@ -1297,7 +1297,7 @@ static const struct command_registration kinetis_ke_command_handler[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver kinetis_ke_flash = {
const struct flash_driver kinetis_ke_flash = {
.name = "kinetis_ke",
.commands = kinetis_ke_command_handler,
.flash_bank_command = kinetis_ke_flash_bank_command,
src/flash/nor/lpc2000.c
+3 -3
View File
@@ -719,7 +719,7 @@ static int lpc2000_iap_working_area_init(struct flash_bank *bank, struct working
int retval = target_write_memory(target, (*iap_working_area)->address, 4, 2, jump_gate);
if (retval != ERROR_OK) {
LOG_ERROR("Write memory at address 0x%8.8" TARGET_PRIxADDR " failed (check work_area definition)",
LOG_ERROR("Write memory at address " TARGET_ADDR_FMT " failed (check work_area definition)",
(*iap_working_area)->address);
target_free_working_area(target, *iap_working_area);
}
@@ -1186,7 +1186,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
free(last_buffer);
}
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("writing 0x%" PRIx32 " bytes to address " TARGET_ADDR_FMT,
thisrun_bytes, bank->base + offset + bytes_written);
/* Write data */
@@ -1609,7 +1609,7 @@ static const struct command_registration lpc2000_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver lpc2000_flash = {
const struct flash_driver lpc2000_flash = {
.name = "lpc2000",
.commands = lpc2000_command_handlers,
.flash_bank_command = lpc2000_flash_bank_command,
src/flash/nor/lpc288x.c
+1 -1
View File
@@ -412,7 +412,7 @@ static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last
return ERROR_OK;
}
struct flash_driver lpc288x_flash = {
const struct flash_driver lpc288x_flash = {
.name = "lpc288x",
.flash_bank_command = lpc288x_flash_bank_command,
.erase = lpc288x_erase,
src/flash/nor/lpc2900.c
+1 -1
View File
@@ -1581,7 +1581,7 @@ static int lpc2900_protect_check(struct flash_bank *bank)
return lpc2900_read_security_status(bank);
}
struct flash_driver lpc2900_flash = {
const struct flash_driver lpc2900_flash = {
.name = "lpc2900",
.commands = lpc2900_command_handlers,
.flash_bank_command = lpc2900_flash_bank_command,
src/flash/nor/lpcspifi.c
+2 -2
View File
@@ -186,7 +186,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
return retval;
}
LOG_DEBUG("Writing algorithm to working area at 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("Writing algorithm to working area at " TARGET_ADDR_FMT,
spifi_init_algorithm->address);
/* Write algorithm to working area */
retval = target_write_buffer(target,
@@ -946,7 +946,7 @@ static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver lpcspifi_flash = {
const struct flash_driver lpcspifi_flash = {
.name = "lpcspifi",
.flash_bank_command = lpcspifi_flash_bank_command,
.erase = lpcspifi_erase,
src/flash/nor/max32xxx.c
+1 -1
View File
@@ -981,7 +981,7 @@ static const struct command_registration max32xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver max32xxx_flash = {
const struct flash_driver max32xxx_flash = {
.name = "max32xxx",
.commands = max32xxx_command_handlers,
.flash_bank_command = max32xxx_flash_bank_command,
src/flash/nor/mdr.c
+1 -1
View File
@@ -609,7 +609,7 @@ static int get_mdr_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver mdr_flash = {
const struct flash_driver mdr_flash = {
.name = "mdr",
.usage = "flash bank <name> mdr <base> <size> 0 0 <target#> <type> <page_count> <sec_count>\n"
"<type>: 0 for main memory, 1 for info memory",
src/flash/nor/mrvlqspi.c
+1 -1
View File
@@ -953,7 +953,7 @@ FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
return ERROR_OK;
}
struct flash_driver mrvlqspi_flash = {
const struct flash_driver mrvlqspi_flash = {
.name = "mrvlqspi",
.flash_bank_command = mrvlqspi_flash_bank_command,
.erase = mrvlqspi_flash_erase,
src/flash/nor/msp432.c
+1 -1
View File
@@ -1075,7 +1075,7 @@ static const struct command_registration msp432_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver msp432_flash = {
const struct flash_driver msp432_flash = {
.name = "msp432",
.commands = msp432_command_handlers,
.flash_bank_command = msp432_flash_bank_command,
src/flash/nor/niietcm4.c
+2 -2
View File
@@ -1585,7 +1585,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
char info_bootflash_addr_str[64];
if (niietcm4_info->bflash_info_remap)
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
"0x%" TARGET_PRIxADDR " base adress", bank->base);
TARGET_ADDR_FMT " base adress", bank->base);
else
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
"not mapped to global adress space");
@@ -1729,7 +1729,7 @@ static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size)
}
struct flash_driver niietcm4_flash = {
const struct flash_driver niietcm4_flash = {
.name = "niietcm4",
.usage = "flash bank <name> niietcm4 <base> <size> 0 0 <target#>",
.commands = niietcm4_command_handlers,
src/flash/nor/nrf5.c
+3 -3
View File
@@ -906,7 +906,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
bank->bank_number = 1;
break;
default:
LOG_ERROR("Invalid bank address 0x%08" TARGET_PRIxADDR, bank->base);
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
@@ -1140,7 +1140,7 @@ static const struct command_registration nrf5_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver nrf5_flash = {
const struct flash_driver nrf5_flash = {
.name = "nrf5",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,
@@ -1158,7 +1158,7 @@ struct flash_driver nrf5_flash = {
/* We need to retain the flash-driver name as well as the commands
* for backwards compatability */
struct flash_driver nrf51_flash = {
const struct flash_driver nrf51_flash = {
.name = "nrf51",
.commands = nrf5_command_handlers,
.flash_bank_command = nrf5_flash_bank_command,
src/flash/nor/numicro.c
+3 -3
View File
@@ -1496,7 +1496,7 @@ static int numicro_erase(struct flash_bank *bank, int first, int last)
return retval;
for (i = first; i <= last; i++) {
LOG_DEBUG("erasing sector %d at address 0x%" TARGET_PRIxADDR, i,
LOG_DEBUG("erasing sector %d at address " TARGET_ADDR_FMT, i,
bank->base + bank->sectors[i].offset);
retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + bank->sectors[i].offset);
if (retval != ERROR_OK)
@@ -1679,7 +1679,7 @@ static int numicro_get_flash_size(struct flash_bank *bank, const struct numicro_
for (size_t i = 0; i < cpu->n_banks; i++) {
if (bank->base == cpu->bank[i].base) {
*flash_size = cpu->bank[i].size;
LOG_INFO("bank base = 0x%08" TARGET_PRIxADDR ", size = 0x%08"
LOG_INFO("bank base = " TARGET_ADDR_FMT ", size = 0x%08"
PRIx32, bank->base, *flash_size);
return ERROR_OK;
}
@@ -1871,7 +1871,7 @@ static const struct command_registration numicro_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver numicro_flash = {
const struct flash_driver numicro_flash = {
.name = "numicro",
.commands = numicro_command_handlers,
.flash_bank_command = numicro_flash_bank_command,
src/flash/nor/ocl.c
+1 -1
View File
@@ -314,7 +314,7 @@ static int ocl_auto_probe(struct flash_bank *bank)
return ERROR_OK;
}
struct flash_driver ocl_flash = {
const struct flash_driver ocl_flash = {
.name = "ocl",
.flash_bank_command = ocl_flash_bank_command,
.erase = ocl_erase,
src/flash/nor/pic32mx.c
+2 -2
View File
@@ -620,7 +620,7 @@ static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("writing to flash at address 0x%08" TARGET_PRIxADDR " at offset 0x%8.8" PRIx32
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
if (offset & 0x3) {
@@ -967,7 +967,7 @@ static const struct command_registration pic32mx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver pic32mx_flash = {
const struct flash_driver pic32mx_flash = {
.name = "pic32mx",
.commands = pic32mx_command_handlers,
.flash_bank_command = pic32mx_flash_bank_command,
src/flash/nor/psoc4.c
+1 -1
View File
@@ -950,7 +950,7 @@ static const struct command_registration psoc4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc4_flash = {
const struct flash_driver psoc4_flash = {
.name = "psoc4",
.commands = psoc4_command_handlers,
.flash_bank_command = psoc4_flash_bank_command,
src/flash/nor/psoc5lp.c
+4 -4
View File
@@ -838,7 +838,7 @@ static const struct command_registration psoc5lp_nvl_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_nvl_flash = {
const struct flash_driver psoc5lp_nvl_flash = {
.name = "psoc5lp_nvl",
.commands = psoc5lp_nvl_command_handlers,
.flash_bank_command = psoc5lp_nvl_flash_bank_command,
@@ -1036,7 +1036,7 @@ static const struct command_registration psoc5lp_eeprom_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_eeprom_flash = {
const struct flash_driver psoc5lp_eeprom_flash = {
.name = "psoc5lp_eeprom",
.commands = psoc5lp_eeprom_command_handlers,
.flash_bank_command = psoc5lp_eeprom_flash_bank_command,
@@ -1227,7 +1227,7 @@ static int psoc5lp_write(struct flash_bank *bank, const uint8_t *buffer,
struct working_area *data_area = even_row ? even_row_area : odd_row_area;
unsigned len = MIN(ROW_SIZE, byte_count);
LOG_DEBUG("Writing load command for array %u row %u at 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("Writing load command for array %u row %u at " TARGET_ADDR_FMT,
array_id, row, data_area->address);
psoc5lp_spc_write_opcode_buffer(target, buf, SPC_LOAD_ROW);
@@ -1548,7 +1548,7 @@ static const struct command_registration psoc5lp_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc5lp_flash = {
const struct flash_driver psoc5lp_flash = {
.name = "psoc5lp",
.commands = psoc5lp_command_handlers,
.flash_bank_command = psoc5lp_flash_bank_command,
src/flash/nor/psoc6.c
+1 -1
View File
@@ -1048,7 +1048,7 @@ static const struct command_registration psoc6_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver psoc6_flash = {
const struct flash_driver psoc6_flash = {
.name = "psoc6",
.commands = psoc6_command_handlers,
.flash_bank_command = psoc6_flash_bank_command,
src/flash/nor/sim3x.c
+1 -1
View File
@@ -1110,7 +1110,7 @@ static const struct command_registration sim3x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver sim3x_flash = {
const struct flash_driver sim3x_flash = {
.name = "sim3x",
.commands = sim3x_command_handlers,
.flash_bank_command = sim3x_flash_bank_command,
src/flash/nor/stellaris.c
+1 -1
View File
@@ -1441,7 +1441,7 @@ static const struct command_registration stellaris_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stellaris_flash = {
const struct flash_driver stellaris_flash = {
.name = "stellaris",
.commands = stellaris_command_handlers,
.flash_bank_command = stellaris_flash_bank_command,
src/flash/nor/stm32f1x.c
+1 -1
View File
@@ -1570,7 +1570,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32f1x_flash = {
const struct flash_driver stm32f1x_flash = {
.name = "stm32f1x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32f2x.c
+212 -11
View File
@@ -123,6 +123,19 @@
/* Mass erase time can be as high as 32 s in x8 mode. */
#define FLASH_MASS_ERASE_TIMEOUT 33000
#define FLASH_BANK_BASE 0x80000000
#define STM32F2_OTP_SIZE 512
#define STM32F2_OTP_SECTOR_SIZE 32
#define STM32F2_OTP_BANK_BASE 0x1fff7800
#define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
/* see RM0410 section 3.6 "One-time programmable bytes" */
#define STM32F7_OTP_SECTOR_SIZE 64
#define STM32F7_OTP_SIZE 1024
#define STM32F7_OTP_BANK_BASE 0x1ff0f000
#define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
#define STM32_FLASH_BASE 0x40023c00
#define STM32_FLASH_ACR 0x40023c00
#define STM32_FLASH_KEYR 0x40023c04
@@ -185,7 +198,8 @@ struct stm32x_options {
struct stm32x_flash_bank {
struct stm32x_options option_bytes;
int probed;
bool probed;
bool otp_unlocked;
bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
bool has_extra_options; /* F42x/43x/469/479/7xx */
bool has_boot_addr; /* F7xx */
@@ -194,6 +208,49 @@ struct stm32x_flash_bank {
uint32_t user_bank_size;
};
static bool stm32x_is_otp(struct flash_bank *bank)
{
return bank->base == STM32F2_OTP_BANK_BASE ||
bank->base == STM32F7_OTP_BANK_BASE;
}
static bool stm32x_otp_is_f7(struct flash_bank *bank)
{
return bank->base == STM32F7_OTP_BANK_BASE;
}
static int stm32x_is_otp_unlocked(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
return stm32x_info->otp_unlocked;
}
static int stm32x_otp_disable(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
LOG_INFO("OTP memory bank #%d is disabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = false;
return ERROR_OK;
}
static int stm32x_otp_enable(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
if (!stm32x_info->otp_unlocked) {
LOG_INFO("OTP memory bank #%d is is enabled for write commands.",
bank->bank_number);
stm32x_info->otp_unlocked = true;
} else {
LOG_WARNING("OTP memory bank #%d is is already enabled for write commands.",
bank->bank_number);
}
return ERROR_OK;
}
/* flash bank stm32x <base> <size> 0 0 <target#>
*/
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
@@ -206,7 +263,8 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
bank->driver_priv = stm32x_info;
stm32x_info->probed = 0;
stm32x_info->probed = false;
stm32x_info->otp_unlocked = false;
stm32x_info->user_bank_size = bank->size;
return ERROR_OK;
@@ -460,14 +518,67 @@ static int stm32x_write_options(struct flash_bank *bank)
return ERROR_OK;
}
static int stm32x_otp_read_protect(struct flash_bank *bank)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
for (i = 0; i < bank->num_sectors; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
bank->sectors[i].is_protected = !lock;
}
return ERROR_OK;
}
static int stm32x_otp_protect(struct flash_bank *bank, int first, int last)
{
struct target *target = bank->target;
uint32_t lock_base;
int i, retval;
uint8_t lock;
assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
: STM32F2_OTP_LOCK_BASE;
for (i = first; first <= last; i++) {
retval = target_read_u8(target, lock_base + i, &lock);
if (retval != ERROR_OK)
return retval;
if (lock)
continue;
lock = 0xff;
retval = target_write_u8(target, lock_base + i, lock);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int stm32x_protect_check(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct flash_sector *prot_blocks;
int num_prot_blocks;
int retval;
/* if it's the OTP bank, look at the lock bits there */
if (stm32x_is_otp(bank))
return stm32x_otp_read_protect(bank);
/* read write protection settings */
int retval = stm32x_read_options(bank);
retval = stm32x_read_options(bank);
if (retval != ERROR_OK) {
LOG_DEBUG("unable to read option bytes");
return retval;
@@ -494,6 +605,11 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
struct target *target = bank->target;
int i;
if (stm32x_is_otp(bank)) {
LOG_ERROR("Cannot erase OTP memory");
return ERROR_FAIL;
}
assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
@@ -553,6 +669,13 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_TARGET_NOT_HALTED;
}
if (stm32x_is_otp(bank)) {
if (!set)
return ERROR_COMMAND_ARGUMENT_INVALID;
return stm32x_otp_protect(bank, first, last);
}
/* read protection settings */
int retval = stm32x_read_options(bank);
if (retval != ERROR_OK) {
@@ -590,6 +713,11 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
#include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
};
if (stm32x_is_otp(bank) && !stm32x_is_otp_unlocked(bank)) {
LOG_ERROR("OTP memory bank is disabled for write commands.");
return ERROR_FAIL;
}
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
@@ -774,7 +902,7 @@ static int setup_sector(struct flash_bank *bank, int start, int num, int size)
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
LOG_DEBUG("sector %d: %d kBytes", i, size >> 10);
}
return start + num;
@@ -828,15 +956,17 @@ static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i, num_prot_blocks;
int i, num_prot_blocks, num_sectors;
uint16_t flash_size_in_kb;
uint16_t otp_size_in_b;
uint16_t otp_sector_size;
uint32_t flash_size_reg = 0x1FFF7A22;
uint16_t max_sector_size_in_kb = 128;
uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t base_address = 0x08000000;
stm32x_info->probed = 0;
stm32x_info->probed = false;
stm32x_info->has_large_mem = false;
stm32x_info->has_boot_addr = false;
stm32x_info->has_extra_options = false;
@@ -856,6 +986,40 @@ static int stm32x_probe(struct flash_bank *bank)
bank->prot_blocks = NULL;
}
/* if explicitely called out as OTP bank, short circuit probe */
if (stm32x_is_otp(bank)) {
if (stm32x_otp_is_f7(bank)) {
otp_size_in_b = STM32F7_OTP_SIZE;
otp_sector_size = STM32F7_OTP_SECTOR_SIZE;
} else {
otp_size_in_b = STM32F2_OTP_SIZE;
otp_sector_size = STM32F2_OTP_SECTOR_SIZE;
}
num_sectors = otp_size_in_b / otp_sector_size;
LOG_INFO("flash size = %d bytes", otp_size_in_b);
assert(num_sectors > 0);
bank->num_sectors = num_sectors;
bank->sectors = calloc(sizeof(struct flash_sector), num_sectors);
if (stm32x_otp_is_f7(bank))
bank->size = STM32F7_OTP_SIZE;
else
bank->size = STM32F2_OTP_SIZE;
for (i = 0; i < num_sectors; i++) {
bank->sectors[i].offset = i * otp_sector_size;
bank->sectors[i].size = otp_sector_size;
bank->sectors[i].is_erased = 1;
bank->sectors[i].is_protected = 0;
}
stm32x_info->probed = true;
return ERROR_OK;
}
/* read stm32 device id register */
int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
@@ -945,7 +1109,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
LOG_INFO("flash size = %d kbytes", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
@@ -1040,7 +1204,7 @@ static int stm32x_probe(struct flash_bank *bank)
bank->num_prot_blocks = num_prot_blocks;
assert((bank->size >> 10) == flash_size_in_kb);
stm32x_info->probed = 1;
stm32x_info->probed = true;
return ERROR_OK;
}
@@ -1483,7 +1647,7 @@ COMMAND_HANDLER(stm32f2x_handle_options_write_command)
/* switching between single- and dual-bank modes requires re-probe */
/* ... and reprogramming of whole flash */
stm32x_info->probed = 0;
stm32x_info->probed = false;
command_print(CMD_CTX, "stm32f2x write options complete.\n"
"INFO: a reset or power cycle is required "
@@ -1533,6 +1697,37 @@ COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
return retval;
}
COMMAND_HANDLER(stm32x_handle_otp_command)
{
if (CMD_ARGC < 2) {
command_print(CMD_CTX, "stm32x otp <bank> (enable|disable|show)");
return ERROR_COMMAND_SYNTAX_ERROR;
}
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
if (stm32x_is_otp(bank)) {
if (strcmp(CMD_ARGV[1], "enable") == 0) {
stm32x_otp_enable(bank);
} else if (strcmp(CMD_ARGV[1], "disable") == 0) {
stm32x_otp_disable(bank);
} else if (strcmp(CMD_ARGV[1], "show") == 0) {
command_print(CMD_CTX,
"OTP memory bank #%d is %s for write commands.",
bank->bank_number,
stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
} else {
return ERROR_COMMAND_SYNTAX_ERROR;
}
} else {
command_print(CMD_CTX, "Failed: not an OTP bank.");
}
return retval;
}
static const struct command_registration stm32x_exec_command_handlers[] = {
{
.name = "lock",
@@ -1576,7 +1771,13 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.usage = "bank_id optcr2",
.help = "Write optcr2 word",
},
{
.name = "otp",
.handler = stm32x_handle_otp_command,
.mode = COMMAND_EXEC,
.usage = "bank_id",
.help = "OTP (One Time Programmable) memory write enable/disable.",
},
COMMAND_REGISTRATION_DONE
};
@@ -1591,7 +1792,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32f2x_flash = {
const struct flash_driver stm32f2x_flash = {
.name = "stm32f2x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32h7x.c
+3 -17
View File
@@ -78,9 +78,6 @@
#define OPT_LOCK (1 << 0)
#define OPT_START (1 << 1)
/* FLASH_OPTCUR bit definitions (reading) */
#define IWDG1_HW (1 << 4)
/* register unlock keys */
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
@@ -109,7 +106,6 @@ struct stm32x_options {
uint8_t user_options;
uint8_t user2_options;
uint8_t user3_options;
uint8_t independent_watchdog_selection;
};
struct stm32h7x_part_info {
@@ -327,11 +323,6 @@ static int stm32x_read_options(struct flash_bank *bank)
stm32x_info->option_bytes.user2_options = (optiondata >> 16) & 0xff;
stm32x_info->option_bytes.user3_options = (optiondata >> 24) & 0x83;
if (optiondata & IWDG1_HW)
stm32x_info->option_bytes.independent_watchdog_selection = 1;
else
stm32x_info->option_bytes.independent_watchdog_selection = 0;
if (stm32x_info->option_bytes.RDP != 0xAA)
LOG_INFO("Device Security Bit Set");
@@ -368,11 +359,6 @@ static int stm32x_write_options(struct flash_bank *bank)
optiondata |= (stm32x_info->option_bytes.user2_options & 0xff) << 16;
optiondata |= (stm32x_info->option_bytes.user3_options & 0x83) << 24;
if (stm32x_info->option_bytes.independent_watchdog_selection)
optiondata |= IWDG1_HW;
else
optiondata &= ~IWDG1_HW;
/* program options */
retval = target_write_u32(target, FLASH_REG_BASE_B0 + FLASH_OPTPRG, optiondata);
if (retval != ERROR_OK)
@@ -833,8 +819,8 @@ static int stm32x_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
} else {
LOG_WARNING("STM32H flash bank base address config is incorrect."
" 0x%" TARGET_PRIxADDR " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
LOG_WARNING("STM32H flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}
@@ -1128,7 +1114,7 @@ static const struct command_registration stm32x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32h7x_flash = {
const struct flash_driver stm32h7x_flash = {
.name = "stm32h7x",
.commands = stm32x_command_handlers,
.flash_bank_command = stm32x_flash_bank_command,
src/flash/nor/stm32l4x.c
+14 -3
View File
@@ -678,8 +678,9 @@ static int stm32l4_probe(struct flash_bank *bank)
/* Invalid FLASH size for this device. */
LOG_WARNING("Invalid flash size for STM32L4+ family device.");
return ERROR_FAIL;
default:
/* Other L4 family devices have 2K pages. */
case 0x461:
case 0x415:
/* These are dual-bank devices, we need to check the OPT_DBANK_LE_1M bit here */
page_size = 2048;
num_pages = flash_size_in_kb / 2;
/* check that calculation result makes sense */
@@ -689,6 +690,16 @@ static int stm32l4_probe(struct flash_bank *bank)
else
stm32l4_info->bank2_start = num_pages / 2;
break;
case 0x462:
case 0x435:
default:
/* These are single-bank devices */
page_size = 2048;
num_pages = flash_size_in_kb / 2;
/* check that calculation result makes sense */
assert(num_pages > 0);
stm32l4_info->bank2_start = UINT16_MAX;
break;
}
/* Release sector table if allocated. */
@@ -1042,7 +1053,7 @@ static const struct command_registration stm32l4_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32l4x_flash = {
const struct flash_driver stm32l4x_flash = {
.name = "stm32l4x",
.commands = stm32l4_command_handlers,
.flash_bank_command = stm32l4_flash_bank_command,
src/flash/nor/stm32lx.c
+3 -3
View File
@@ -816,8 +816,8 @@ static int stm32lx_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
} else {
LOG_WARNING("STM32L flash bank base address config is incorrect."
" 0x%" TARGET_PRIxADDR " but should rather be 0x%" PRIx32
LOG_WARNING("STM32L flash bank base address config is incorrect. "
TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
" or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
@@ -944,7 +944,7 @@ static const struct command_registration stm32lx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver stm32lx_flash = {
const struct flash_driver stm32lx_flash = {
.name = "stm32lx",
.commands = stm32lx_command_handlers,
.flash_bank_command = stm32lx_flash_bank_command,
src/flash/nor/stmsmi.c
+3 -3
View File
@@ -559,13 +559,13 @@ static int stmsmi_probe(struct flash_bank *bank)
stmsmi_info->bank_num = SMI_SEL_BANK3;
break;
default:
LOG_ERROR("Invalid SMI base address 0x%" TARGET_PRIxADDR, bank->base);
LOG_ERROR("Invalid SMI base address " TARGET_ADDR_FMT, bank->base);
return ERROR_FAIL;
}
io_base = target_device->io_base;
stmsmi_info->io_base = io_base;
LOG_DEBUG("Valid SMI on device %s at address 0x%" TARGET_PRIxADDR,
LOG_DEBUG("Valid SMI on device %s at address " TARGET_ADDR_FMT,
target_device->name, bank->base);
/* read and decode flash ID; returns in SW mode */
@@ -652,7 +652,7 @@ static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver stmsmi_flash = {
const struct flash_driver stmsmi_flash = {
.name = "stmsmi",
.flash_bank_command = stmsmi_flash_bank_command,
.erase = stmsmi_erase,
src/flash/nor/str7x.c
+1 -1
View File
@@ -799,7 +799,7 @@ static const struct command_registration str7x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str7x_flash = {
const struct flash_driver str7x_flash = {
.name = "str7x",
.commands = str7x_command_handlers,
.flash_bank_command = str7x_flash_bank_command,
src/flash/nor/str9x.c
+1 -1
View File
@@ -667,7 +667,7 @@ static const struct command_registration str9x_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str9x_flash = {
const struct flash_driver str9x_flash = {
.name = "str9x",
.commands = str9x_command_handlers,
.flash_bank_command = str9x_flash_bank_command,
src/flash/nor/str9xpec.c
+1 -1
View File
@@ -1195,7 +1195,7 @@ static const struct command_registration str9xpec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver str9xpec_flash = {
const struct flash_driver str9xpec_flash = {
.name = "str9xpec",
.commands = str9xpec_command_handlers,
.flash_bank_command = str9xpec_flash_bank_command,
src/flash/nor/tcl.c
+12 -15
View File
@@ -112,7 +112,7 @@ COMMAND_HANDLER(handle_flash_info_command)
LOG_WARNING("Flash protection check is not implemented.");
command_print(CMD_CTX,
"#%d : %s at 0x%8.8" TARGET_PRIxADDR ", size 0x%8.8" PRIx32
"#%d : %s at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32
", buswidth %i, chipwidth %i",
p->bank_number,
p->driver->name,
@@ -177,7 +177,7 @@ COMMAND_HANDLER(handle_flash_probe_command)
retval = p->driver->probe(p);
if (retval == ERROR_OK)
command_print(CMD_CTX,
"flash '%s' found at 0x%8.8" TARGET_PRIxADDR,
"flash '%s' found at " TARGET_ADDR_FMT,
p->driver->name,
p->base);
} else {
@@ -205,8 +205,8 @@ COMMAND_HANDLER(handle_flash_erase_check_command)
command_print(CMD_CTX, "successfully checked erase state");
else {
command_print(CMD_CTX,
"unknown error when checking erase state of flash bank #%s at 0x%8.8"
TARGET_PRIxADDR,
"unknown error when checking erase state of flash bank #%s at "
TARGET_ADDR_FMT,
CMD_ARGV[0],
p->base);
}
@@ -240,7 +240,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
{
struct flash_bank *p;
int retval = ERROR_OK;
uint32_t address;
target_addr_t address;
uint32_t length;
bool do_pad = false;
bool do_unlock = false;
@@ -263,7 +263,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
if (CMD_ARGC != 2)
return ERROR_COMMAND_SYNTAX_ERROR;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
if (length <= 0) {
@@ -289,7 +289,8 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
retval = flash_erase_address_range(target, do_pad, address, length);
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
command_print(CMD_CTX, "erased address 0x%8.8" PRIx32 " (length %" PRIi32 ")"
command_print(CMD_CTX, "erased address " TARGET_ADDR_FMT " (length %"
PRIi32 ")"
" in %fs (%0.3f KiB/s)", address, length,
duration_elapsed(&bench), duration_kbps(&bench, length));
}
@@ -485,11 +486,7 @@ COMMAND_HANDLER(handle_flash_fill_command)
if (CMD_ARGC != 3)
return ERROR_COMMAND_SYNTAX_ERROR;
#if BUILD_TARGET64
COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], address);
#else
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
#endif
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
@@ -1110,7 +1107,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
}
const char *driver_name = CMD_ARGV[0];
struct flash_driver *driver = flash_driver_find_by_name(driver_name);
const struct flash_driver *driver = flash_driver_find_by_name(driver_name);
if (NULL == driver) {
/* no matching flash driver found */
LOG_ERROR("flash driver '%s' not found", driver_name);
@@ -1149,7 +1146,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
int retval;
retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
if (ERROR_OK != retval) {
LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" TARGET_PRIxADDR
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
"; usage: %s", driver_name, c->base, driver->usage);
free(c);
return retval;
@@ -1170,7 +1167,7 @@ COMMAND_HANDLER(handle_flash_banks_command)
unsigned n = 0;
for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++) {
LOG_USER("#%d : %s (%s) at 0x%8.8" TARGET_PRIxADDR ", size 0x%8.8" PRIx32 ", "
LOG_USER("#%d : %s (%s) at " TARGET_ADDR_FMT ", size 0x%8.8" PRIx32 ", "
"buswidth %u, chipwidth %u", p->bank_number,
p->name, p->driver->name, p->base, p->size,
p->bus_width, p->chip_width);
src/flash/nor/tms470.c
+6 -6
View File
@@ -165,8 +165,8 @@ static int tms470_read_part_info(struct flash_bank *bank)
part_name = "TMS470R1A256";
if (bank->base >= 0x00040000) {
LOG_ERROR("No %s flash bank contains base address 0x%08"
TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address "
TARGET_ADDR_FMT ".",
part_name,
bank->base);
return ERROR_FLASH_OPERATION_FAILED;
@@ -205,7 +205,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS,
sizeof(TMS470R1A288_BANK1_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -245,7 +245,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
(void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS,
sizeof(TMS470R1A384_BANK2_SECTORS));
} else {
LOG_ERROR("No %s flash bank contains base address 0x%08" TARGET_PRIxADDR ".",
LOG_ERROR("No %s flash bank contains base address " TARGET_ADDR_FMT ".",
part_name, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -901,7 +901,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
tms470_read_part_info(bank);
LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" TARGET_PRIxADDR,
LOG_INFO("Writing %" PRId32 " bytes starting at " TARGET_ADDR_FMT,
count, bank->base + offset);
/* set GLBCTRL.4 */
@@ -1162,7 +1162,7 @@ FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
return ERROR_OK;
}
struct flash_driver tms470_flash = {
const struct flash_driver tms470_flash = {
.name = "tms470",
.commands = tms470_command_handlers,
.flash_bank_command = tms470_flash_bank_command,
src/flash/nor/virtual.c
+2 -2
View File
@@ -185,7 +185,7 @@ static int virtual_info(struct flash_bank *bank, char *buf, int buf_size)
if (master_bank == NULL)
return ERROR_FLASH_OPERATION_FAILED;
snprintf(buf, buf_size, "%s driver for flash bank %s at 0x%8.8" TARGET_PRIxADDR,
snprintf(buf, buf_size, "%s driver for flash bank %s at " TARGET_ADDR_FMT,
bank->driver->name, master_bank->name, master_bank->base);
return ERROR_OK;
@@ -224,7 +224,7 @@ static int virtual_flash_read(struct flash_bank *bank,
return ERROR_OK;
}
struct flash_driver virtual_flash = {
const struct flash_driver virtual_flash = {
.name = "virtual",
.flash_bank_command = virtual_flash_bank_command,
.erase = virtual_erase,
src/flash/nor/w600.c
+1 -1
View File
@@ -376,7 +376,7 @@ static int get_w600_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
struct flash_driver w600_flash = {
const struct flash_driver w600_flash = {
.name = "w600",
.flash_bank_command = w600_flash_bank_command,
.erase = w600_erase,
src/flash/nor/xcf.c
+1 -1
View File
@@ -881,7 +881,7 @@ static const struct command_registration xcf_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xcf_flash = {
const struct flash_driver xcf_flash = {
.name = "xcf",
.usage = NULL,
.commands = xcf_command_handlers,
src/flash/nor/xmc1xxx.c
+2 -2
View File
@@ -305,7 +305,7 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
uint32_t addr = bank->base + offset;
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" TARGET_PRIxADDR,
LOG_DEBUG("copying %" PRId32 " bytes to SRAM " TARGET_ADDR_FMT,
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
data_workarea->address);
@@ -534,7 +534,7 @@ static const struct command_registration xmc1xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xmc1xxx_flash = {
const struct flash_driver xmc1xxx_flash = {
.name = "xmc1xxx",
.commands = xmc1xxx_command_handlers,
.flash_bank_command = xmc1xxx_flash_bank_command,
src/flash/nor/xmc4xxx.c
+2 -2
View File
@@ -778,7 +778,7 @@ static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
memcpy(&tmp_buf[start_pad], buffer, remaining);
if (end_pad) {
LOG_INFO("Padding end of page @%08" TARGET_PRIxADDR " by %d bytes",
LOG_INFO("Padding end of page @" TARGET_ADDR_FMT " by %d bytes",
bank->base + offset, end_pad);
memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
}
@@ -1343,7 +1343,7 @@ static const struct command_registration xmc4xxx_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
struct flash_driver xmc4xxx_flash = {
const struct flash_driver xmc4xxx_flash = {
.name = "xmc4xxx",
.commands = xmc4xxx_command_handlers,
.flash_bank_command = xmc4xxx_flash_bank_command,