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commit fb7009fc38eff2f169385589e0f71ca4f9626cb2
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 16:41:14 2018 -0800

    Make some error messages to be printed once

commit e09dd62229bd2c152bf403e601aa098e29aaa850
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 15:30:10 2018 -0800

    Reduce severity of the error messages that are polluting the log

commit 73b6ea55ebefd004bef71359d611d3a887b89983
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Fri Feb 23 13:32:54 2018 -0800

    removed unused variable

commit c3bdcb0c4ae63bb5afad628c58eb29fe43c9646d
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 18:32:08 2018 -0800

    more R/O checks

commit 353cf212bd892bbb065e6a57fb9412cc8fea0548
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Thu Feb 22 14:27:25 2018 -0800

    write progbuf via DMI

commit e73d82e3d6cf064d0323e3c686f3b7710f42a51f
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 18:47:36 2018 -0800

    add writes to progbuf

commit f97e4b53e4064ae4e7807a1aac74c5d92aea7666
Author: Gleb Gagarin <gleb@sifive.com>
Date:   Wed Feb 21 16:20:12 2018 -0800

    Try to zero out ROM
This commit is contained in:
Megan Wachs
2018-04-12 15:02:04 -07:00
parent 1b37f60969
commit 7eca2dfe5d
1 changed files with 25 additions and 3 deletions
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src/target/riscv/riscv-013.c
+25 -3
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@@ -383,7 +383,11 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
int retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("dmi_scan failed jtag scan");
static int once = 1;
if (once) {
LOG_ERROR("dmi_scan failed jtag scan");
once = 0;
}
return DMI_STATUS_FAILED;
}
@@ -418,13 +422,22 @@ static uint32_t dmi_read(struct target *target, uint16_t address)
} else if (status == DMI_STATUS_SUCCESS) {
break;
} else {
LOG_ERROR("failed read from 0x%x, status=%d", address, status);
static int once = 1;
if (once) {
LOG_ERROR("failed read from 0x%x, status=%d", address, status);
once = 0;
}
break;
}
usleep(100000);
}
if (status != DMI_STATUS_SUCCESS) {
LOG_ERROR("Failed read from 0x%x; status=%d", address, status);
static int once = 1;
if (once) {
LOG_INFO("Failed read from 0x%x; status=%d", address, status);
once = 0;
}
return ~0;
}
@@ -2268,6 +2281,9 @@ int riscv013_test_compliance(struct target *target) {
dmstatus = dmi_read(target, DMI_DMSTATUS);
} while ((dmstatus & DMI_DMSTATUS_ALLHALTED) == 0);
dmi_write(target, DMI_DMSTATUS, 0xffffffff);
COMPLIANCE_TEST(dmi_read(target, DMI_DMSTATUS) == dmstatus, "DMSTATUS is R/O");
// resumereq. This will resume the hart but this test is destructive anyway.
dmcontrol &= ~DMI_DMCONTROL_HALTREQ;
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1);
@@ -2340,6 +2356,12 @@ int riscv013_test_compliance(struct target *target) {
}
COMPLIANCE_TEST(dmi_read(target, DMI_HALTSUM) == expected_haltsum, "HALTSUM should report all halted harts");
dmi_write(target, DMI_HALTSUM, 0xffffffff);
COMPLIANCE_TEST(dmi_read(target, DMI_HALTSUM) == expected_haltsum, "HALTSUM is R/O");
dmi_write(target, DMI_HALTSUM, 0x0);
COMPLIANCE_TEST(dmi_read(target, DMI_HALTSUM) == expected_haltsum, "HALTSUM is R/O");
for (int i = 0; i < riscv_count_harts(target); i +=32){
uint32_t haltstat = dmi_read(target, 0x40 + (i / 32));
uint32_t haltstat_expected = (((i + 1) * 32) <= riscv_count_harts(target)) ? 0xFFFFFFFFU : ((1U << (riscv_count_harts(target) % 32)) - 1);