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jtagspi: new protocol that includes transfer length

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This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:

1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:

  The previous logic was erroneous. The delay in clock cyles from a bit
  written to the jtag interface to a bit read by the jtag interface is:

  * The number of BYPASSed TAPs before this (jtagspi) tap
  * The length of the jtagspi data register (1)
  * The number of BYPASSed TAPs before this one.

  I.e. it is just the number of enabled TAPs. This also gets rid of the
  configuration parameter DR_LENGTH.

3. Use marker bit to start spi transfer

  If there are TAPs ahead of this one on the JTAG chain, and we are in
  DR-SHIFT, there will be old bits toggled through first before the first
  valid bit destined for the flash.
  This delays the begin of the JTAGSPI transaction until the first high bit.

4. New jtagspi protocol

  A JTAGSPI transfer now consists of:

  * an arbitrary number of 0 bits (from BYPASS registers in front of the
    JTAG2SPI DR)
  * a marker bit (1) indicating the start of the JTAG2SPI transaction
  * 32 bits (big endian) describing the length of the SPI transaction
  * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
  * an arbitrary number of cycles (to shift MISO/TDO data through
    subsequent BYPASS registers)

5. xilinx_bscan_spi: clean up, add ultrascale

This is tested on the following configurations:

* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
  adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
  Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E

Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Robert Jordens
2017-08-08 18:16:35 +02:00
committed by Paul Fertser
parent 22ad1c0f60
commit 867bdb2e92
4 changed files with 342 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
src/flash/nor/jtagspi.c
View File

@@ -32,14 +32,13 @@ struct jtagspi_flash_bank {
const struct flash_device *dev;
int probed;
uint32_t ir;
uint32_t dr_len;
};
FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
{
struct jtagspi_flash_bank *info;
if (CMD_ARGC < 8)
if (CMD_ARGC < 7)
return ERROR_COMMAND_SYNTAX_ERROR;
info = malloc(sizeof(struct jtagspi_flash_bank));
@@ -52,7 +51,6 @@ FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
info->tap = NULL;
info->probed = 0;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->dr_len);
return ERROR_OK;
}
@@ -63,9 +61,6 @@ static void jtagspi_set_ir(struct flash_bank *bank)
struct scan_field field;
uint8_t buf[4];
if (buf_get_u32(info->tap->cur_instr, 0, info->tap->ir_length) == info->ir)
return;
LOG_DEBUG("loading jtagspi ir");
buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
field.num_bits = info->tap->ir_length;
@@ -84,28 +79,53 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
uint32_t *addr, uint8_t *data, int len)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
struct scan_field fields[3];
uint8_t cmd_buf[4];
struct scan_field fields[6];
uint8_t marker = 1;
uint8_t xfer_bits_buf[4];
uint8_t addr_buf[3];
uint8_t *data_buf;
uint32_t xfer_bits;
int is_read, lenb, n;
/* LOG_DEBUG("cmd=0x%02x len=%i", cmd, len); */
n = 0;
fields[n].num_bits = 8;
cmd_buf[0] = cmd;
if (addr) {
h_u24_to_be(cmd_buf + 1, *addr);
fields[n].num_bits += 24;
}
flip_u8(cmd_buf, cmd_buf, 4);
fields[n].out_value = cmd_buf;
fields[n].in_value = NULL;
n++;
is_read = (len < 0);
if (is_read)
len = -len;
n = 0;
fields[n].num_bits = 1;
fields[n].out_value = &marker;
fields[n].in_value = NULL;
n++;
xfer_bits = 8 + len - 1;
/* cmd + read/write - 1 due to the counter implementation */
if (addr)
xfer_bits += 24;
h_u32_to_be(xfer_bits_buf, xfer_bits);
flip_u8(xfer_bits_buf, xfer_bits_buf, 4);
fields[n].num_bits = 32;
fields[n].out_value = xfer_bits_buf;
fields[n].in_value = NULL;
n++;
cmd = flip_u32(cmd, 8);
fields[n].num_bits = 8;
fields[n].out_value = &cmd;
fields[n].in_value = NULL;
n++;
if (addr) {
h_u24_to_be(addr_buf, *addr);
flip_u8(addr_buf, addr_buf, 3);
fields[n].num_bits = 24;
fields[n].out_value = addr_buf;
fields[n].in_value = NULL;
n++;
}
lenb = DIV_ROUND_UP(len, 8);
data_buf = malloc(lenb);
if (lenb > 0) {
@@ -114,10 +134,11 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
return ERROR_FAIL;
}
if (is_read) {
fields[n].num_bits = info->dr_len;
fields[n].num_bits = jtag_tap_count_enabled();
fields[n].out_value = NULL;
fields[n].in_value = NULL;
n++;
fields[n].out_value = NULL;
fields[n].in_value = data_buf;
} else {
@@ -130,6 +151,7 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
}
jtagspi_set_ir(bank);
/* passing from an IR scan to SHIFT-DR clears BYPASS registers */
jtag_add_dr_scan(info->tap, n, fields, TAP_IDLE);
jtag_execute_queue();