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Remove annoying end-of-line whitespace from most src/*

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files; omitted src/httpd


git-svn-id: svn://svn.berlios.de/openocd/trunk@2742 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
dbrownell
2009-09-21 18:40:55 +00:00
parent 0bcf5a6b76
commit 86a7d813a1
20 changed files with 183 additions and 183 deletions
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2
src/target/Makefile.am
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@@ -98,7 +98,7 @@ noinst_HEADERS = \
avrt.h
nobase_dist_pkglib_DATA =
nobase_dist_pkglib_DATA += xscale/debug_handler.bin
nobase_dist_pkglib_DATA += xscale/debug_handler.bin
nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
MAINTAINERCLEANFILES = $(srcdir)/Makefile.in

2
src/target/arm11.c
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@@ -1066,7 +1066,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
retval = arm11_simulate_step(target, &next_pc);
if (retval != ERROR_OK)
return retval;
brp[0].value = next_pc;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
}

6
src/target/arm7_9_common.c
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@@ -95,7 +95,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
{
LOG_ERROR("BUG: no hardware comparator available");
}
LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
breakpoint->unique_id,
breakpoint->address,
breakpoint->set );
@@ -158,7 +158,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
return ERROR_FAIL;
}
LOG_DEBUG("SW BP using hw wp: %d",
LOG_DEBUG("SW BP using hw wp: %d",
arm7_9->sw_breakpoints_added );
return jtag_execute_queue();
@@ -371,7 +371,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->type == BKPT_HARD)
{
LOG_DEBUG("BPID: %d Releasing hw wp: %d",
LOG_DEBUG("BPID: %d Releasing hw wp: %d",
breakpoint->unique_id,
breakpoint->set );
if (breakpoint->set == 1)

4
src/target/arm926ejs.c
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@@ -174,12 +174,12 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C
{
return retval;
}
if (buf_get_u32(&access, 0, 1) == 1)
{
break;
}
/* 10ms timeout */
if ((timeval_ms()-then)>10)
{

12
src/target/breakpoints.c
View File

@@ -54,7 +54,7 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
{
n++;
if (breakpoint->address == address){
LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)",
LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)",
address, breakpoint->unique_id );
return ERROR_OK;
}
@@ -76,10 +76,10 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)",
LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)",
breakpoint_type_strings[(*breakpoint_p)->type],
(*breakpoint_p)->unique_id );
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
@@ -87,7 +87,7 @@ int breakpoint_add(target_t *target, uint32_t address, uint32_t length, enum bre
break;
case ERROR_TARGET_NOT_HALTED:
LOG_INFO("can't add breakpoint while target is running (BPID: %d)",
(*breakpoint_p)->unique_id );
(*breakpoint_p)->unique_id );
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
@@ -207,7 +207,7 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)",
LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)",
watchpoint_rw_strings[(*watchpoint_p)->rw],
(*watchpoint_p)->unique_id );
free (*watchpoint_p);
@@ -230,7 +230,7 @@ int watchpoint_add(target_t *target, uint32_t address, uint32_t length, enum wat
LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 " of length 0x%8.8x (WPID: %d)",
watchpoint_rw_strings[(*watchpoint_p)->rw],
(*watchpoint_p)->address,
(*watchpoint_p)->address,
(*watchpoint_p)->length,
(*watchpoint_p)->unique_id );

8
src/target/cortex_a8.c
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@@ -138,8 +138,8 @@ int cortex_a8_init_debug_access(target_t *target)
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
/* Enabling of instruction execution in debug mode is done in debug_entry code */
/* Enabling of instruction execution in debug mode is done in debug_entry code */
return retval;
}
@@ -1374,7 +1374,7 @@ int cortex_a8_examine(struct target_s *target)
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1451,7 +1451,7 @@ int cortex_a8_examine(struct target_s *target)
/* Configure core debug access */
cortex_a8_init_debug_access(target);
target->type->examined = 1;
return retval;

14
src/target/mips_m4k.c
View File

@@ -524,7 +524,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
}
@@ -612,7 +612,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
comparator_list[bp_num].used = 0;
comparator_list[bp_num].bp_value = 0;
target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
}
else
{
@@ -711,9 +711,9 @@ int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
* and exclude both load and store accesses from watchpoint
* condition evaluation
*/
int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
(0xff << EJTAG_DBCn_BLM_SHIFT);
if (watchpoint->set)
{
LOG_WARNING("watchpoint already set");
@@ -765,7 +765,7 @@ int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
return ERROR_OK;
}
@@ -774,7 +774,7 @@ int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
/* get pointers to arch-specific information */
mips32_common_t *mips32 = target->arch_info;
mips32_comparator_t * comparator_list = mips32->data_break_list;
if (!watchpoint->set)
{
LOG_WARNING("watchpoint not set");
@@ -804,7 +804,7 @@ int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
LOG_INFO("no hardware watchpoints available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
mips32->num_data_bpoints_avail--;
mips_m4k_set_watchpoint(target, watchpoint);

2
src/target/target.c
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@@ -1241,7 +1241,7 @@ int target_read_buffer(struct target_s *target, uint32_t address, uint32_t size,
address += aligned;
size -= aligned;
}
/*prevent byte access when possible (avoid AHB access limitations in some cases)*/
if(size >=2)
{

2
src/target/target.h
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@@ -42,7 +42,7 @@ struct command_context_s;
* TARGET_RESET = 3: the target is being held in reset (only a temporary state,
* not sure how this is used with all the recent changes)
* TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
* behalf of the debugger (e.g. algorithm for flashing)
* behalf of the debugger (e.g. algorithm for flashing)
*
* also see: target_state_name();
*/

70
src/target/xscale/debug_handler.S
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@@ -30,7 +30,7 @@
1:
mrc p14, 0, r15, c14, c0, 0
bvs 1b
mcr p14, 0, \reg, c8, c0, 0
mcr p14, 0, \reg, c8, c0, 0
.endm
@ receive word from debugger
@@ -38,7 +38,7 @@
1:
mrc p14, 0, r15, c14, c0, 0
bpl 1b
mrc p14, 0, \reg, c9, c0, 0
mrc p14, 0, \reg, c9, c0, 0
.endm
@ save register on debugger, small
@@ -75,7 +75,7 @@ reset_handler:
mrc p14, 0, r13, c10, c0
@ check if global enable bit (GE) is set
ands r13, r13, #0x80000000
bne debug_handler
@ set global enable bit (GE)
@@ -111,7 +111,7 @@ debug_handler:
cmp r1, #MODE_USR
bne not_user_mode
@ replace USR mode with SYS
bic r0, r0, #MODE_MASK
orr r0, r0, #MODE_SYS
@@ -124,7 +124,7 @@ not_user_mode:
@ wait for command from debugger, than execute desired function
get_command:
bl receive_from_debugger
@ 0x0n - register access
cmp r0, #0x0
beq get_banked_registers
@@ -145,10 +145,10 @@ get_command:
@ 0x2n - write memory
cmp r0, #0x21
beq write_byte
cmp r0, #0x22
beq write_half_word
cmp r0, #0x24
beq write_word
@@ -172,7 +172,7 @@ get_command:
cmp r0, #0x51
beq invalidate_d_cache
cmp r0, #0x52
beq invalidate_i_cache
@@ -185,10 +185,10 @@ get_command:
cmp r0, #0x61
beq read_trace_buffer
cmp r0, #0x62
beq clean_trace_buffer
@ return (back to get_command)
b get_command
@@ -221,11 +221,11 @@ resume:
m_receive_from_debugger lr
@ branch back to application code, restoring CPSR
subs pc, lr, #0
subs pc, lr, #0
@ get banked registers
@ receive mode bits from host, then run into save_banked_registers to
@ receive mode bits from host, then run into save_banked_registers to
get_banked_registers:
bl receive_from_debugger
@@ -239,7 +239,7 @@ save_banked_registers:
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ backup banked registers
m_send_to_debugger r8
m_send_to_debugger r9
@@ -251,7 +251,7 @@ save_banked_registers:
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_save
@ backup SPSR
@@ -271,8 +271,8 @@ no_spsr_to_save:
@ set banked registers
@ receive mode bits from host, then run into save_banked_registers to
@ receive mode bits from host, then run into save_banked_registers to
set_banked_registers:
bl receive_from_debugger
@@ -286,7 +286,7 @@ restore_banked_registers:
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ set banked registers
m_receive_from_debugger r8
m_receive_from_debugger r9
@@ -298,7 +298,7 @@ restore_banked_registers:
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_restore
@ set SPSR
@@ -327,7 +327,7 @@ read_byte:
rb_loop:
ldrb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
@@ -335,7 +335,7 @@ rb_loop:
subs r1, r1, #1
bne rb_loop
@ return
b get_command
@@ -352,7 +352,7 @@ read_half_word:
rh_loop:
ldrh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
@@ -360,7 +360,7 @@ rh_loop:
subs r1, r1, #1
bne rh_loop
@ return
b get_command
@@ -377,7 +377,7 @@ read_word:
rw_loop:
ldr r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
@@ -385,7 +385,7 @@ rw_loop:
subs r1, r1, #1
bne rw_loop
@ return
b get_command
@@ -409,7 +409,7 @@ wb_loop:
subs r1, r1, #1
bne wb_loop
@ return
b get_command
@@ -433,7 +433,7 @@ wh_loop:
subs r1, r1, #1
bne wh_loop
@ return
b get_command
@@ -457,7 +457,7 @@ ww_loop:
subs r1, r1, #1
bne ww_loop
@ return
b get_command
@@ -466,7 +466,7 @@ ww_loop:
clear_sa:
@ read DCSR
mrc p14, 0, r0, c10, c0
@ clear SA bit
bic r0, r0, #0x20
@@ -481,7 +481,7 @@ clear_sa:
clean_d_cache:
@ r0: cache clean area
bl receive_from_debugger
mov r1, #1024
clean_loop:
mcr p15, 0, r0, c7, c2, 5
@@ -568,7 +568,7 @@ read_cp_table:
b read_cp_reg_reply
read_cp_reg_reply:
bl send_to_debugger
bl send_to_debugger
@ return
b get_command
@@ -641,14 +641,14 @@ read_tb_loop:
@ dump checkpoint register 0
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
bl send_to_debugger
@ dump checkpoint register 1
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
bl send_to_debugger
@ return
b get_command
@ ----
clean_trace_buffer:
@@ -662,7 +662,7 @@ clean_tb_loop:
@ return
b get_command
@ ----
@@ -697,7 +697,7 @@ resume_w_trace:
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
@ branch back to application code, restoring CPSR
subs pc, lr, #0
subs pc, lr, #0
undef_handler:
swi_handler:

4
src/target/xscale/debug_handler.cmd
View File

@@ -2,14 +2,14 @@
ENTRY(reset_handler)
/* specify the mini-ICache memory areas */
MEMORY
MEMORY
{
mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */
mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */
}
/* now define the output sections */
SECTIONS
SECTIONS
{
.part1 :
{