flash/stm32l4x: support STM32WBA5xx devices

STM32WBA5x have a single bank flash up to 1MB Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com> Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7694 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-31 15:16:35 +01:00
parent fb52ba4fa1
commit 870769b0ba
3 changed files with 132 additions and 0 deletions
--- a/tcl/target/stm32wbax.cfg
+++ b/tcl/target/stm32wbax.cfg
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbax family
+
+#
+# stm32wba devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME stm32wbax
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    if { [using_jtag] } {
+        set _CPUTAPID 0x6ba00477
+    } else {
+        # SWD IDCODE (single drop, arm)
+        set _CPUTAPID 0x6ba02477
+    }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+    jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+    jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with HSION | HSIRDY.
+    # Use HSI 16 MHz clock, compliant even with VOS == 2.
+    # 1 WS compliant with VOS == 2 and 16 MHz.
+    mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+    mmw 0x56020C00 0x00000100 0x00000000	;# RCC_CR |= HSION
+    mmw 0x56020C1C 0x00000000 0x00000002	;# RCC_CFGR1: SW=HSI16
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is HSI (16 MHz)
+    adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+    mmw 0xE0042004 0x00000006 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"