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ARM: setup "secure monitor mode" shadow regs

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Teach the "armv4_5" register code to understand about the
secure monitor mode:

 - Add the other three shadowed registers to the arrays
 - Support another internal mode number (sigh) in mappings
 - Catch malloc/calloc failures building that register cache

This should kick in for Cortex-A8 and ARM1176.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-11-18 13:23:00 -08:00
parent bbebfd9e13
commit 8a6d4ced4c
2 changed files with 53 additions and 21 deletions
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5
src/target/armv4_5.h
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@@ -56,7 +56,7 @@ typedef enum armv4_5_state
extern char* armv4_5_state_strings[];
extern const int armv4_5_core_reg_map[7][17];
extern const int armv4_5_core_reg_map[8][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
@@ -69,7 +69,8 @@ enum
ARMV4_5_SPSR_IRQ = 33,
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 39,
};
#define ARMV4_5_COMMON_MAGIC 0x0A450A45