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topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc

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This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Sergio Chico
2013-11-10 16:03:40 +01:00
committed by Andreas Fritiofson
parent 2d64cf92ae
commit 93a3a82e49
7 changed files with 95 additions and 6 deletions
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3
src/target/openrisc/Makefile.am
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@@ -7,7 +7,8 @@ OPENRISC_SRC = \
or1k.c \
or1k_du_adv.c \
or1k_tap_mohor.c \
or1k_tap_vjtag.c
or1k_tap_vjtag.c \
or1k_tap_xilinx_bscan.c
noinst_HEADERS = \
or1k.h \