topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc

This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

src/target/openrisc/or1k.c

@@ -1179,6 +1179,7 @@ static int or1k_target_create(struct target *target, Jim_Interp *interp)
 	or1k_create_reg_list(target);
 
 	or1k_tap_vjtag_register();
+	or1k_tap_xilinx_bscan_register();
 	or1k_tap_mohor_register();
 
 	or1k_du_adv_register();