topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc

This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

tcl/board/or1k_generic.cfg

@@ -1,6 +1,9 @@
-# If you want to use the VJTAG TAP, you must set your FPGA TAP ID here
+# If you want to use the VJTAG TAP or the XILINX BSCAN,
+# you must set your FPGA TAP ID here
+
 set FPGATAPID 0x020b30dd
-# Choose your TAP core (VJTAG or MOHOR)
+
+# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
 set TAP_TYPE VJTAG
 # Set your chip name
 set CHIPNAME or1200