Rolf Meeser <rolfm_9dq@yahoo.de> adds flash support for NXP's LPC2900 family (ARM968E).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2715 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe
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# Hitex eval board for LPC2929/LPC2939
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# http://www.hitex.com/
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# Delays on reset lines
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jtag_nsrst_delay 50
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jtag_ntrst_delay 1
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# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
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# Adaptive clocking through RTCK is not supported.
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jtag_khz 2000
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# Target device: LPC29xx with ETB
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# The following variables are used by the LPC2900 script:
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# HAS_ETB Must be set to 1. The CPU on this board has ETB.
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# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
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set HAS_ETB 1
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set FLASH_CLOCK 112000
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source [find target/lpc2900.cfg]
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# A working area will help speeding the flash programming
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#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
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$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
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# Event handlers
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$_TARGETNAME configure -event reset-start {
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# Back to the slow JTAG clock
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jtag_khz 2000
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}
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# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
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flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
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$_TARGETNAME configure -event reset-init {
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# Flash
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mww 0x20200010 0x00000007 # FBWST: 7 wait states, not chached
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# Use PLL
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mww 0xFFFF8020 0x00000001 # XTAL_OSC_CONTROL: enable, 1-20 MHz
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mww 0xFFFF8070 0x01000000 # SYS_CLK_CONF: Crystal
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mww 0xFFFF8028 0x00000005 # PLL: (power down)
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mww 0xFFFF8028 0x01060004 # PLL: M=7, 2P=2 (power up)
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# --> f=112 MHz, fcco=224 MHz
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sleep 100
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mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
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# Increase JTAG speed
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jtag_khz 6000
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# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
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mww 0xE0001138 0x0000001F # P1.14 = D0
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mww 0xE000113C 0x0000001F # P1.15 = D1
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mww 0xE0001140 0x0000001F # P1.16 = D2
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mww 0xE0001144 0x0000001F # P1.17 = D3
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mww 0xE0001148 0x0000001F # P1.18 = D4
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mww 0xE000114C 0x0000001F # P1.19 = D5
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mww 0xE0001150 0x0000001F # P1.20 = D6
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mww 0xE0001154 0x0000001F # P1.21 = D7
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mww 0xE0001200 0x0000001F # P2.0 = D8
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mww 0xE0001204 0x0000001F # P2.1 = D9
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mww 0xE0001208 0x0000001F # P2.2 = D10
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mww 0xE000120C 0x0000001F # P2.3 = D11
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mww 0xE0001210 0x0000001F # P2.4 = D12
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mww 0xE0001214 0x0000001F # P2.5 = D13
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mww 0xE0001218 0x0000001F # P2.6 = D14
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mww 0xE000121C 0x0000001F # P2.7 = D15
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mww 0xE0001104 0x00000007 # P1.1 = A1
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mww 0xE0001108 0x00000007 # P1.2 = A2
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mww 0xE000110C 0x00000007 # P1.3 = A3
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mww 0xE0001110 0x00000007 # P1.4 = A4
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mww 0xE0001114 0x00000007 # P1.5 = A5
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mww 0xE0001118 0x00000007 # P1.6 = A6
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mww 0xE000111C 0x00000007 # P1.7 = A7
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mww 0xE0001028 0x00000007 # P0.10 = A8
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mww 0xE000102C 0x00000007 # P0.11 = A9
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mww 0xE0001030 0x00000007 # P0.12 = A10
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mww 0xE0001034 0x00000007 # P0.13 = A11
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mww 0xE0001038 0x00000007 # P0.14 = A12
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mww 0xE000103C 0x00000007 # P0.15 = A13
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mww 0xE0001048 0x00000007 # P0.18 = A14
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mww 0xE000104C 0x00000007 # P0.19 = A15
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mww 0xE0001050 0x00000007 # P0.20 = A16
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mww 0xE0001054 0x00000007 # P0.21 = A17
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mww 0xE0001058 0x00000007 # P0.22 = A18
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mww 0xE000105C 0x00000007 # P0.23 = A19
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mww 0xE0001238 0x00000007 # P2.14 = BLS0
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mww 0xE000123C 0x00000007 # P2.15 = BLS1
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mww 0xE0001300 0x00000007 # P3.0 = CS6
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mww 0xE0001304 0x00000007 # P3.1 = CS7
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mww 0xE0001130 0x00000007 # P1.12 = OE_N
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mww 0xE0001134 0x00000007 # P1.13 = WE_N
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mww 0x600000BC 0x00000041 # Bank6 16-bit mode, RBLE=1
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mww 0x600000B4 0x00000000 # Bank6 WSTOEN=0
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mww 0x600000AC 0x00000005 # Bank6 WST1=5
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mww 0x600000B8 0x00000001 # Bank6 WSTWEN=1
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mww 0x600000B0 0x00000006 # Bank6 WST2=6
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mww 0x600000A8 0x00000002 # Bank6 IDCY=2
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mww 0x600000D8 0x00000041 # Bank7 16-bit mode, RBLE=1
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mww 0x600000D0 0x00000000 # Bank7 WSTOEN=0
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mww 0x600000C8 0x0000000A # Bank7 WST1=10
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mww 0x600000D4 0x00000001 # Bank7 WSTWEN=1
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mww 0x600000CC 0x0000000C # Bank7 WST2=8
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mww 0x600000C4 0x00000002 # Bank7 IDCY=2
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}
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@@ -0,0 +1,65 @@
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc2900
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0596802B
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}
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if { [info exists HAS_ETB ] } {
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} else {
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# Set default (no ETB).
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# Show a warning, because this should have been configured explicitely.
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set HAS_ETB 0
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# TODO warning?
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}
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if { [info exists ETBTAPID ] } {
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set _ETBTAPID $ETBTAPID
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} else {
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set _ETBTAPID 0x1B900F0F
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}
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# TRST and SRST both exist, and can be controlled independently
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reset_config trst_and_srst separate
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# Define the _TARGETNAME
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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# Include the ETB tap controller if asked for.
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# Has to be done manually for newer devices (not an "old" LPC2917/2919).
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if { $HAS_ETB == 1 } {
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# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
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set HAS_ETB 0
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# Add the ETB tap controller and the ARM9 core debug tap
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jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# Create the ".cpu" target
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target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
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# Configure ETM and ETB
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etm config $_TARGETNAME 8 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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} else {
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# Add the ARM9 core debug tap
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# Create the ".cpu" target
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target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
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}
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arm7_9 dbgrq enable
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arm7_9 dcc_downloads enable
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# Flash bank configuration:
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# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
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# Flash base address, total flash size, and number of sectors are all configured automatically.
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flash bank lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
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