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Add support for vector register access (#448)

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* WIP

Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd

* Reading v* registers appears to work.

Can't really test it though, because gdb doesn't print them right.

Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5

* Total hack to communicate registers to gdb.

Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765

* Implement writing vector registers.

Fixed reading vector registers.

Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214

* Show gdb the actual size of the vector registers.

This length may be different per hart.

Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493

* Remove outdated todo comment.

Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128

* Removed TODO comment.

Filed #449 to track this.

Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47

* Nicely handle some errors reading/writing V regs.

Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
This commit is contained in:
Tim Newsome
2020-02-14 14:54:05 -08:00
committed by GitHub
parent 7cb8843794
commit 95462a8a35
7 changed files with 1776 additions and 51 deletions
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src/target/riscv/program.c
+2 -1
View File
@@ -56,7 +56,8 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
if (riscv_program_ebreak(p) != ERROR_OK) {
LOG_ERROR("Unable to write ebreak");
for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, (long)p->debug_buffer[i], (long)p->debug_buffer[i]);
LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i,
(long)p->debug_buffer[i], (long)p->debug_buffer[i]);
return ERROR_FAIL;
}