rename jtag_khz as adapter_khz
Globally rename "jtag_khz" as "adapter_khz", and move it out of the "jtag" command group ... it needs to be used with non-JTAG transports Includes a migration aid (in jtag/startup.tcl) so that old user scripts won't break. That aid should Sunset in about a year. (We may want to update it to include a nag message too.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
@@ -65,4 +65,4 @@ $_TARGETNAME configure -event reset-init {
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}
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# This target is pretty snappy...
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jtag_khz 16000
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adapter_khz 16000
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@@ -15,7 +15,7 @@ flash_bank cfi 0x10000000 0x00200000 2 2 0
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proc at91rm9200_dk_init { } {
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# Try to run at 1khz... Yea, that slow!
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# Chip is really running @ 32khz
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jtag_khz 8
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adapter_khz 8
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mww 0xfffffc64 0xffffffff
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## disable all clocks but system clock
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@@ -41,7 +41,7 @@ proc at91rm9200_dk_init { } {
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#========================================
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# CPU now runs at 180mhz
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# SYS runs at 60mhz.
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jtag_khz 40000
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adapter_khz 40000
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#========================================
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@@ -77,7 +77,7 @@ proc at91sam9g20_init { } {
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# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
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# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
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jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
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adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
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halt # Make sure processor is halted, or error will result in following steps.
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mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
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@@ -112,7 +112,7 @@ proc at91sam9g20_init { } {
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# Switch over to adaptive clocking.
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jtag_khz 0
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adapter_khz 0
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# Enable faster DCC downloads.
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@@ -19,7 +19,7 @@ if { [info exists ETM_DRIVER] } {
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proc csb337_clk_init { } {
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# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
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jtag_khz 8
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adapter_khz 8
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# CKGR_MOR: start main oscillator (3.6864 MHz)
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mww 0xfffffc20 0xff01
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@@ -37,7 +37,7 @@ proc csb337_clk_init { } {
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sleep 20
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# CPU is in Normal Mode ... allows faster JTAG clock speed
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jtag_khz 40000
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adapter_khz 40000
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}
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proc csb337_nor_init { } {
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@@ -103,7 +103,7 @@ proc dm365evm_init {} {
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echo "Initialize DM365 EVM board"
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# CLKIN = 24 MHz ... can't talk quickly to ARM yet
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jtag_khz 1500
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adapter_khz 1500
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# FIXME -- PLL init
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@@ -4,7 +4,7 @@
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# http://www.luminarymicro.com/products/lm3s1968_evaluation_kits.html
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# NOTE: to use J-Link instead of the on-board interface,
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# you may also need to reduce jtag_khz to be about 1200.
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# you may also need to reduce adapter_khz to be about 1200.
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# source [find interface/jlink.cfg]
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# include the FT2232 interface config for on-board JTAG interface
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@@ -14,7 +14,7 @@ source [find interface/luminary.cfg]
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source [find target/lm3s1968.cfg]
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# jtag speed
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jtag_khz 3000
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adapter_khz 3000
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jtag_nsrst_delay 100
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@@ -10,7 +10,7 @@ source [find interface/luminary.cfg]
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source [find target/lm3s811.cfg]
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# jtag speed
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jtag_khz 500
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adapter_khz 500
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jtag_nsrst_delay 100
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@@ -9,7 +9,7 @@ source [find interface/luminary-icdi.cfg]
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source [find target/lm3s9b9x.cfg]
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# jtag speed
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jtag_khz 500
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adapter_khz 500
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jtag_nsrst_delay 100
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@@ -26,7 +26,7 @@ jtag_ntrst_delay 300
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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jtag_khz 16000
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adapter_khz 16000
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# Target events
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@@ -7,7 +7,7 @@ jtag_ntrst_delay 1
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# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
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# Adaptive clocking through RTCK is not supported.
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jtag_khz 2000
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adapter_khz 2000
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# Target device: LPC29xx with ETB
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# The following variables are used by the LPC2900 script:
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@@ -24,7 +24,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
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# Event handlers
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$_TARGETNAME configure -event reset-start {
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# Back to the slow JTAG clock
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jtag_khz 2000
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adapter_khz 2000
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}
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# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
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@@ -46,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
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mww 0xFFFF8070 0x02000000 # SYS_CLK_CONF: PLL
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# Increase JTAG speed
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jtag_khz 6000
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adapter_khz 6000
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# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
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mww 0xE0001138 0x0000001F # P1.14 = D0
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@@ -5,7 +5,7 @@
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source [find interface/hitex_str9-comstick.cfg]
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# set jtag speed
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jtag_khz 3000
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adapter_khz 3000
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jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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@@ -8,7 +8,7 @@ proc imx27lnst_init { } {
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# This setup puts RAM at 0xA0000000
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# reset the board correctly
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jtag_khz 500
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adapter_khz 500
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reset run
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reset halt
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@@ -121,7 +121,7 @@ reset_config trst_and_srst
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# IMPORTANT! See README at top of this file.
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#-------------------------------------------------------------------------
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jtag_khz 12000
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adapter_khz 12000
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jtag interface
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#-------------------------------------------------------------------------
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@@ -2,7 +2,7 @@ source [find target/lpc3250.cfg]
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jtag_nsrst_delay 200
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jtag_ntrst_delay 1
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jtag_khz 200
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adapter_khz 200
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reset_config trst_and_srst separate
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arm7_9 dcc_downloads enable
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@@ -11,11 +11,11 @@ $_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-start {
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arm7_9 fast_memory_access disable
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jtag_khz 200
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adapter_khz 200
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}
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$_TARGETNAME configure -event reset-end {
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jtag_khz 6000
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adapter_khz 6000
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arm7_9 fast_memory_access enable
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}
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+2
-2
@@ -26,11 +26,11 @@ reset_config trst_and_srst separate
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# issue telnet: reset init
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# issue gdb: monitor reset init
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$_TARGETNAME configure -event reset-init {
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jtag_khz 100
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adapter_khz 100
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# this will setup Telo board
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setupTelo
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#turn up the JTAG speed
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jtag_khz 3000
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adapter_khz 3000
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puts "JTAG speek now 3MHz"
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puts "type helpC100 to get help on C100"
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}
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@@ -99,7 +99,7 @@ proc topas910_init { } {
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mww 0xf4300004 0x00000000
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sleep 10
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# jtag_khz NNNN
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# adapter_khz NNNN
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# remap off in case of IROM boot
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mww 0xf0000004 0x00000001
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@@ -105,7 +105,7 @@ proc topasa900_init { } {
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mww 0xf4300004 0x00000000
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sleep 10
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# jtag_khz NNNN
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# adapter_khz NNNN
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# remap off in case of IROM boot
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mww 0xf0000004 0x00000001
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@@ -66,7 +66,7 @@ $_TARGETNAME configure -event reset-init {
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# other things than flash programming.
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$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
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jtag_khz 16000
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adapter_khz 16000
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proc production_info {} {
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