Halt should work now.
This commit is contained in:
Tim Newsome
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,155 @@
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#include "encoding.h"
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#define S0 8
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#define S1 9
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static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
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return (value >> lo) & ((1 << (hi+1-lo)) - 1);
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}
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static uint32_t bit(uint32_t value, unsigned int b) {
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return (value >> b) & 1;
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}
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static uint32_t jal(unsigned int rd, uint32_t imm) {
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return (bit(imm, 20) << 31) |
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(bits(imm, 10, 1) << 21) |
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(bit(imm, 11) << 20) |
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(bits(imm, 19, 12) << 12) |
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(rd << 7) |
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MATCH_JAL;
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}
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static uint32_t csrsi(unsigned int csr, uint16_t imm) {
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return (csr << 20) |
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(bits(imm, 4, 0) << 15) |
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MATCH_CSRRSI;
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}
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/*
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static uint32_t csrci(unsigned int csr, uint16_t imm) {
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return (csr << 20) |
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(bits(imm, 4, 0) << 15) |
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MATCH_CSRRCI;
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}
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static uint32_t csrr(unsigned int rd, unsigned int csr) {
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return (csr << 20) | (rd << 7) | MATCH_CSRRS;
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}
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static uint32_t csrw(unsigned int source, unsigned int csr) {
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return (csr << 20) | (source << 15) | MATCH_CSRRW;
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}
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static uint32_t fence_i(void)
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{
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return MATCH_FENCE_I;
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}
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static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SB;
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}
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static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SH;
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}
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static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(src << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SW;
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}
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static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(bits(src, 4, 0) << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_SD;
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}
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static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LD;
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}
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static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LW;
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}
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static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LH;
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}
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static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 0) << 20) |
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(base << 15) |
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(bits(rd, 4, 0) << 7) |
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MATCH_LB;
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}
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static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(bits(src, 4, 0) << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_FSD;
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}
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static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(bits(src, 4, 0) << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_FLD;
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}
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static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
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{
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return (bits(imm, 11, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_ADDI;
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}
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static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
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{
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return (bits(imm, 11, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_ORI;
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}
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static uint32_t nop(void)
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{
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return addi(0, 0, 0);
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}
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*/
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@@ -0,0 +1,278 @@
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#include <assert.h>
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "target.h"
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#include "target_type.h"
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#include "log.h"
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#include "jtag/jtag.h"
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#include "opcodes.h"
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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#define DEBUG_ROM_START 0x800
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#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
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#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
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#define DEBUG_RAM_START 0x400
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/*** JTAG registers. ***/
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#define DTMINFO 0x10
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#define DTMINFO_ADDRBITS (0xf<<4)
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#define DTMINFO_VERSION (0xf)
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#define DBUS 0x11
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/*** Debug Bus registers. ***/
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#define DMCONTROL 0x10
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#define DMCONTROL_HALTNOT (1L<<33)
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#define DMCONTROL_INTERRUPT (1L<<32)
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#define DMCONTROL_BUSERROR (7<<19)
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#define DMCONTROL_SERIAL (3<<16)
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#define DMCONTROL_AUTOINCREMENT (1<<15)
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#define DMCONTROL_ACCESS (7<<12)
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#define DMCONTROL_HARTID (0x3ff<<2)
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define DMINFO 0x11
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#define DMINFO_ABUSSIZE (0x7f<<25)
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#define DMINFO_SERIALCOUNT (0xf<<21)
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#define DMINFO_ACCESS128 (1<<20)
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#define DMINFO_ACCESS64 (1<<19)
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#define DMINFO_ACCESS32 (1<<18)
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#define DMINFO_ACCESS16 (1<<17)
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#define DMINFO_ACCESS8 (1<<16)
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#define DMINFO_DRAMSIZE (0x3f<<10)
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#define DMINFO_AUTHENTICATED (1<<5)
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#define DMINFO_AUTHBUSY (1<<4)
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#define DMINFO_AUTHTYPE (3<<2)
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#define DMINFO_VERSION 3
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/*** Info about the core being debugged. ***/
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#define DBUS_ADDRESS_UNKNOWN 0xffff
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typedef struct {
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/* Number of address bits in the dbus register. */
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uint8_t addrbits;
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/* Width of a GPR (and many other things) in bits. */
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uint8_t xlen;
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/* Last value we wrote to DBUS_ADDRESS (eg. the address of the register
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* whose value will be read the next time we scan dbus). */
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uint16_t dbus_address;
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/* Number of words in Debug RAM. */
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unsigned int dramsize;
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/* Our local copy of Debug RAM. */
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uint32_t *dram;
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/* One bit for every word in dram. If the bit is set, then we're
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* confident that the value we have matches the one in actual Debug
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* RAM. */
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uint64_t dram_valid;
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} riscv_info_t;
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/*** Utility functions. ***/
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static uint64_t dbus_scan(struct target *target, uint16_t address,
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uint64_t data_out, bool read, bool write)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct scan_field field;
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uint8_t in[8];
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uint8_t out[8];
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assert(info->addrbits != 0);
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// TODO: max bits is 32?
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field.num_bits = info->addrbits + 35;
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field.out_value = out;
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if (read) {
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field.in_value = in;
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}
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buf_set_u64(out, 0, 34, data_out);
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buf_set_u64(out, 34, info->addrbits, address);
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buf_set_u64(out, info->addrbits + 34, 1, write);
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(target->tap, 1, &field, TAP_DRUPDATE);
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info->dbus_address = address;
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return buf_get_u64(in, 0, 34);
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}
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static uint64_t dbus_read(struct target *target, uint16_t address, uint16_t next_address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (address != info->dbus_address) {
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dbus_scan(target, address, 0, false, false);
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}
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return dbus_scan(target, next_address, 0, true, false);
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}
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static uint64_t dbus_write(struct target *target, uint16_t address, uint64_t value)
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{
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return dbus_scan(target, address, value, false, true);
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}
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static uint32_t dtminfo_read(struct target *target)
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{
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struct scan_field field;
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uint8_t in[4];
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uint8_t out[4];
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field.num_bits = target->tap->ir_length;
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field.out_value = out;
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field.in_value = NULL;
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buf_set_u32(out, 0, field.num_bits, DTMINFO);
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jtag_add_ir_scan(target->tap, &field, TAP_DRSELECT);
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = in;
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jtag_add_dr_scan(target->tap, 1, &field, TAP_DRUPDATE);
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/* Always return to dbus. */
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/* TODO: Can we rely on IR not being messed with between calls into
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* RISCV code? Eg. what happens if there are multiple cores and some
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* other core is accessed? */
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field.num_bits = target->tap->ir_length;
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field.out_value = out;
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field.in_value = NULL;
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buf_set_u32(out, 0, field.num_bits, DBUS);
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jtag_add_ir_scan(target->tap, &field, TAP_DRSELECT);
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return buf_get_u32(field.in_value, 0, 32);
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}
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static void dram_write32(struct target *target, unsigned int index, uint32_t value,
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bool set_interrupt)
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{
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// TODO: check cache to see this even needs doing.
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uint16_t address;
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if (index < 0x10)
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address = index;
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else
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address = 0x40 + index - 0x10;
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uint64_t dbus_value = DMCONTROL_HALTNOT | value;
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if (set_interrupt)
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dbus_value |= DMCONTROL_INTERRUPT;
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dbus_write(target, address, dbus_value);
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}
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/* Write instruction that jumps from the specified word in Debug RAM to resume
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* in Debug ROM. */
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static void dram_write_jump(struct target *target, unsigned int index, bool set_interrupt)
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{
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dram_write32(target, index,
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
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set_interrupt);
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}
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/*** OpenOCD target functions. ***/
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static int riscv_init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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target->arch_info = calloc(1, sizeof(riscv_info_t));
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if (!target->arch_info)
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return ERROR_FAIL;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->dbus_address = DBUS_ADDRESS_UNKNOWN;
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return ERROR_OK;
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}
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static void riscv_deinit_target(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (info->dram) {
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free(info->dram);
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}
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free(info);
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target->arch_info = NULL;
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}
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static int riscv_examine(struct target *target)
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{
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if (target_was_examined(target)) {
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return ERROR_OK;
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}
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uint32_t dtminfo = dtminfo_read(target);
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->addrbits = get_field(dtminfo, DTMINFO_ADDRBITS);
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uint32_t dminfo = dbus_read(target, DMINFO, 0);
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info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
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info->dram = malloc(info->dramsize * 4);
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if (!info->dram)
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return ERROR_FAIL;
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info->dram_valid = 0;
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if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
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LOG_ERROR("Authentication required by RISC-V core but not "
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"supported by OpenOCD. dminfo=0x%x", dminfo);
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return ERROR_FAIL;
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}
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target_set_examined(target);
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return ERROR_OK;
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}
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static int riscv_poll(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint64_t value;
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if (info->dbus_address < 0x10 || info->dbus_address == DMCONTROL) {
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value = dbus_read(target, info->dbus_address, 0);
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} else {
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value = dbus_read(target, 0, 0);
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}
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bool haltnot = get_field(value, DMCONTROL_HALTNOT);
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bool interrupt = get_field(value, DMCONTROL_INTERRUPT);
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if (haltnot && interrupt) {
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target->state = TARGET_DEBUG_RUNNING;
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} else if (haltnot && !interrupt) {
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target->state = TARGET_HALTED;
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} else if (!haltnot && interrupt) {
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// Target is halting. There is no state for that, so don't change anything.
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} else if (!haltnot && !interrupt) {
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target->state = TARGET_RUNNING;
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}
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return ERROR_OK;
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}
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static int riscv_halt(struct target *target)
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{
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dram_write32(target, 0, csrsi(CSR_DCSR, DCSR_HALT), false);
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dram_write_jump(target, 1, true);
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return ERROR_OK;
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}
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struct target_type riscv_target = {
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.name = "riscv",
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.init_target = riscv_init_target,
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.deinit_target = riscv_deinit_target,
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.examine = riscv_examine,
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/* poll current target status */
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.poll = riscv_poll,
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.halt = riscv_halt,
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/* TODO: */
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/* .virt2phys = riscv_virt2phys, */
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};
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