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Merge branch 'master' into from_upstream

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Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8
This commit is contained in:
Tim Newsome
2019-09-27 12:07:00 -07:00
parent bbdc28e0f5 3110092720
commit 9aac179cf2
194 changed files with 3445 additions and 4571 deletions
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tcl/target/arm_corelink_sse200.cfg
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#
# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
#
global TARGET
set TARGET $_CHIPNAME
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
#
# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
# We will configure work area assuming 8-KB bank size in SRAM bank 1.
# Also SRAM start addresses defaults to secure mode alias.
# These values can be overridden as per board configuration
#
global _WORKAREASIZE_CPU0
if { [info exists WORKAREASIZE_CPU0] } {
set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
} else {
set _WORKAREASIZE_CPU0 0x1000
}
global _WORKAREAADDR_CPU0
if { [info exists WORKAREAADDR_CPU0] } {
set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
} else {
set _WORKAREAADDR_CPU0 0x30008000
}
#
# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
# Core 0 is the boot core and will always be configured.
#
target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
${TARGET}.CPU0 cortex_m reset_config sysresetreq
#
# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
# Core 1 is optional and locked at boot until core 0 unlocks it.
#
if { $_ENABLE_CPU1 } {
global _WORKAREASIZE_CPU1
if { [info exists WORKAREASIZE_CPU1] } {
set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
} else {
set _WORKAREASIZE_CPU1 0x1000
}
global _WORKAREAADDR_CPU1
if { [info exists WORKAREAADDR_CPU1] } {
set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
} else {
set _WORKAREAADDR_CPU1 0x30009000
}
target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
${TARGET}.CPU1 cortex_m reset_config vectreset
}
# Make sure the default target is the boot core
targets ${TARGET}.CPU0
tcl/target/atsaml1x.cfg
+31
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@@ -0,0 +1,31 @@
#
# Microchip (formerly Atmel) SAM L1x target
#
# Note: These devices support SWD only.
#
transport select swd
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME saml1x
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
swd newdap $_CHIPNAME cpu -expected-id 0x0bf11477
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
if {![using_hla]} {
cortex_m reset_config sysresetreq
}
tcl/target/imx6.cfg
+32 -10
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@@ -1,4 +1,10 @@
# Freescale i.MX6 series single/dual/quad core processor
#
# Freescale i.MX6 series
#
# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
#
# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -8,9 +14,9 @@ if { [info exists CHIPNAME] } {
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
@@ -20,18 +26,34 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
# List supported SJC TAPIDs from imx reference manuals:
set _SJC_TAPID_6Q 0x0191c01d
set _SJC_TAPID_6D 0x0191e01d
set _SJC_TAPID_6QP 0x3191c01d
set _SJC_TAPID_6DP 0x3191d01d
set _SJC_TAPID_6DL 0x0891a01d
set _SJC_TAPID_6S 0x0891b01d
set _SJC_TAPID_6SL 0x0891f01d
set _SJC_TAPID_6SLL 0x088c201d
# Allow external override of the first SJC TAPID
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0191c01d
set _SJC_TAPID $_SJC_TAPID_6Q
}
set _SJC_TAPID2 0x2191c01d
set _SJC_TAPID3 0x2191e01d
set _SJC_TAPID4 0x1191c01d
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
-ignore-version \
-expected-id $_SJC_TAPID \
-expected-id $_SJC_TAPID_6QP \
-expected-id $_SJC_TAPID_6DP \
-expected-id $_SJC_TAPID_6D \
-expected-id $_SJC_TAPID_6DL \
-expected-id $_SJC_TAPID_6S \
-expected-id $_SJC_TAPID_6SL \
-expected-id $_SJC_TAPID_6SLL
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
tcl/target/imx6sx.cfg
+50
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@@ -0,0 +1,50 @@
#
# Freescale i.MX6SoloX
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx6sx
}
# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0891c01d
}
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -ignore-version
# Cortex-A9 (boot core)
target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
-coreid 0 -dbgbase 0x82150000
# Cortex-M4 (default off)
target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
-ap-num 0 -defer-examine
# AHB mem-ap target
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
# Default target is Cortex-A9
targets $_CHIPNAME.cpu_a9
tcl/target/imx6ul.cfg
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@@ -0,0 +1,50 @@
#
# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx6ul
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
set _SJC_TAPID_6UL 0x0891d01d
set _SJC_TAPID_6ULL 0x0891e01d
set _SJC_TAPID_6ULZ 0x1891e01d
# Allow external override of the first SJC TAPID
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID $_SJC_TAPID_6UL
}
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-ignore-version \
-expected-id $_SJC_TAPID \
-expected-id $_SJC_TAPID_6ULL \
-expected-id $_SJC_TAPID_6ULZ \
# Create DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# Main AHB bus
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
# Cortex-A7 single core
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000
tcl/target/imx7.cfg
+5
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@@ -37,4 +37,9 @@ set _TARGETNAME_2 $_CHIPNAME.cpu_m4
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \
-defer-examine
#
# AHB mem-ap target
#
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
targets $_TARGETNAME.0
tcl/target/imx7ulp.cfg
+36
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@@ -0,0 +1,36 @@
#
# NXP i.MX7ULP: Cortex-A7 + Cortex-M4
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx7ulp
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
# TAPID is from FreeScale!
set _DAP_TAPID 0x188e101d
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# Cortex-A7
target create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80030000
# Cortex-M4
# Boots by default so don't defer examination
target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3
# AHB main soc bus
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
# Default is Cortex-A7
targets $_CHIPNAME.cpu_a7
tcl/target/imx8m.cfg
+8 -2
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@@ -52,7 +52,13 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
}
eval $_smp_command
targets $_TARGETNAME.0
# declare the auxiliary Cortex-M4 core on AP #4
target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4
target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
-defer-examine
# AHB-AP for direct access to soc bus
target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
# default target is A53 core 0
targets $_TARGETNAME.0
tcl/target/psoc4.cfg
+1 -1
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@@ -179,7 +179,7 @@ proc ocd_process_reset_inner { MODE } {
}
# Check if PSoC CPU is stopped in system ROM
set pc [ocd_reg pc]
set pc [reg pc]
regsub {pc[^:]*: } $pc "" pc
if { $pc < 0x10000000 || $pc > 0x1000ffff } {
set hint ""
tcl/target/renesas_r7s72100.cfg
+25
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@@ -0,0 +1,25 @@
# Renesas R-Car RZ/A1H
# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME r7s72100
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
# Configuring only one core using DAP.
# Base addresses of cores:
# core 0 - 0x80030000
set _TARGETNAME $_CHIPNAME.ca9
dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
target create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000
targets ${_TARGETNAME}
tcl/target/renesas_rcar_gen3.cfg
+4 -4
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@@ -47,17 +47,17 @@ switch $_soc {
set _num_cr7 1
set _boot_core CA57
}
V3H {
V3M {
set _CHIPNAME r8a77970
set _num_ca57 0
set _num_ca53 4
set _num_ca53 2
set _num_cr7 1
set _boot_core CA53
}
V3M {
V3H {
set _CHIPNAME r8a77980
set _num_ca57 0
set _num_ca53 2
set _num_ca53 4
set _num_cr7 1
set _boot_core CA53
}
tcl/target/stm32f7x.cfg
+13
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@@ -51,6 +51,19 @@ set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
# also address 0x00200000 via the ITCM. The former mapping is read-write in
# hardware, while the latter is read-only. By presenting an alias, we
# accomplish two things:
# (1) We allow writing at 0x00200000 (because the alias acts identically to the
# original bank), which allows code intended to run from that address to
# also be linked for loading at that address, simplifying linking.
# (2) We allow the proper memory map to be delivered to GDB, which will cause
# it to use hardware breakpoints at the 0x00200000 mapping (correctly
# identifying it as Flash), which it would otherwise not do. Configuring
# the Flash via ITCM alias as virtual
flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
adapter_khz 2000
tcl/target/swm050.cfg
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@@ -0,0 +1,45 @@
# Synwit SWM050
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME swm050
}
set _CHIPSERIES swm050
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x400
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x410CC200
}
swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
$_TARGETNAME configure -event reset-init {
# Stop the watchdog, just to be safe
mww 0x40019000 0x00
# Set clock divider value to 1
mww 0x400F0000 0x01
# Set system clock to 18Mhz
mww 0x400F0008 0x00
}
# SWM050 (Cortex-M0 core) supports SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}