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tcl: move STM32 MPU files in vendor folder

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Move the existing files for STM32MP13x and STM32MP15x in the
folder "st".
Rename the board files using the correct names.
While there, add the missing URL to one of the boards.

Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8982
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
This commit is contained in:
Antonio Borneo
2025-07-04 16:50:46 +02:00
parent 1f56ea647d
commit 9bb6fa67ca
5 changed files with 5 additions and 2 deletions
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102
tcl/target/st/stm32mp13x.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# STMicroelectronics STM32MP13x (Single Cortex-A7)
# http://www.st.com/stm32mp1
# HLA does not support custom CSW nor AP other than 0
if { [using_hla] } {
echo "ERROR: HLA transport cannot work with this target."
echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
shutdown
}
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32mp13x
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x6ba00477
} else {
set _CPUTAPID 0x6ba02477
}
}
# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
set _CLCTAPID $CLCTAPID
} else {
set _CLCTAPID 0x06501041
}
swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
if { [using_jtag] } {
jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
# NOTE: keep ap-num and dbgbase to speed-up examine after reset
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
$_CHIPNAME.cpu cortex_a maskisr on
$_CHIPNAME.cpu cortex_a dacrfixup on
# interface does not work while srst is asserted
# this is target specific, valid for every board
# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
reset_config srst_gates_jtag srst_pulls_trst
adapter speed 5000
adapter srst pulse_width 200
# bootrom has an internal timeout of 1 second for detecting the boot flash.
# wait at least 1 second to guarantee we are out of bootrom
adapter srst delay 1100
add_help_text axi_secure "Set secure mode for following AXI accesses"
proc axi_secure {} {
$::_CHIPNAME.dap apsel 0
$::_CHIPNAME.dap apcsw 0x10006000
}
add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
proc axi_nsecure {} {
$::_CHIPNAME.dap apsel 0
$::_CHIPNAME.dap apcsw 0x30006000
}
axi_secure
proc dbgmcu_enable_debug {} {
# keep clock enabled in low-power
## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
# freeze watchdog 1 and 2 on core halted
catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
}
proc toggle_cpu_dbg_claim0 {} {
# toggle CPU0 DBG_CLAIM[0]
$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
}
# FIXME: most of handlers below will be removed once reset framework get merged
$_CHIPNAME.ap1 configure -event reset-deassert-pre {
adapter deassert srst deassert trst
catch {dap init}
catch {$::_CHIPNAME.dap apid 1}
}
$_CHIPNAME.cpu configure -event reset-deassert-pre {$::_CHIPNAME.cpu arp_examine}
$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
$_CHIPNAME.ap1 configure -event examine-start {dap init}
$_CHIPNAME.ap1 configure -event examine-end {dbgmcu_enable_debug}