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fix syntax of mww phys.

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This commit is contained in:
Øyvind Harboe
2009-10-25 18:29:17 +01:00
parent d785f552ee
commit a07422c26c
5 changed files with 44 additions and 44 deletions
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22
tcl/target/davinci.cfg
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@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
mww phys [expr $timer2_phys + 0x28] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
arm926ejs mww phys [expr $timer2_phys + 0x20] 0
mww phys [expr $timer2_phys + 0x20] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
arm926ejs mww phys [expr $timer2_phys + 0x24] 0
arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
mww phys [expr $timer2_phys + 0x24] 0
mww phys [expr $timer2_phys + 0x24] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
arm926ejs mww phys [expr $timer2_phys + 0x10] 0
arm926ejs mww phys [expr $timer2_phys + 0x14] 0
arm926ejs mww phys [expr $timer2_phys + 0x18] 0
arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
mww phys [expr $timer2_phys + 0x10] 0
mww phys [expr $timer2_phys + 0x14] 0
mww phys [expr $timer2_phys + 0x18] 0
mww phys [expr $timer2_phys + 0x1c] 0
# WDTCR: put into pre-active state, then active
arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
mww phys [expr $timer2_phys + 0x28] 0xa5c64000
mww phys [expr $timer2_phys + 0x28] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
mww phys [expr $timer2_phys + 0x28] 0x00004000
}