auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

jtag: drivers: xlnx-axi-xvc: Add support for Xilinx XVC over direct bus interface (AXI)

Browse Source 
This change allow to use direct mapping of the JTAG interface using
Xilinx Virtual Cable (XVC) over AXI. This merges the existing XVC PCIe
code and the patch proposed by Jeremy Garff
(https://review.openocd.org/c/openocd/+/6594).

This is useful when using on a Zynq/ZynqMP/uBlaze host with direct
access to the debug bridge over AXI.  You can then use the debug bridge
Xilinx IP (AXIXVC) to debug a remote device.

Signed-off-by: Nicolas Derumigny <nicolas.derumigny@inria.fr>
Change-Id: I934591b489e30b400b87772b1437e6030440904c
Reviewed-on: https://review.openocd.org/c/openocd/+/8595
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Nicolas Derumigny
2024-11-05 15:49:04 +00:00
committed by Antonio Borneo
parent 8cdf8cb995
commit a192949095
6 changed files with 455 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
doc/openocd.texi
View File

@@ -613,6 +613,12 @@ emulation model of target hardware.
@item @b{xlnx_pcie_xvc}
@* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
@* Link: @url{https://www.xilinx.com/products/intellectual-property/debug-bridge.html}
@item @b{xlnx_axi_xvc}
@* A JTAG driver exposing JTAG to OpenOCD over AXI-mapped registers.
@* Link: @url{https://docs.amd.com/r/en-US/pg437-axi-jtag/Introduction}
@* Link: @url{https://china.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf}
@item @b{linuxspidev}
@* A SPI based SWD driver using Linux SPI devices.
@@ -3352,6 +3358,21 @@ The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
@end deffn
@end deffn
@deffn {Interface Driver} {xlnx_axi_xvc}
This driver supports the Xilinx JTAG mapping over AXI using the AXI to JTAG
Converter or the AXI-to-JTAG mode of the debug bridge.
It is commonly found in Xilinx MPSoC based designs. It allows debugging
fabric based JTAG/SWD devices such as Cortex-M1/M3 or RISC-V softcores. Access to this
is exposed via extended capability registers in the AXI-mapped configuration space.
@deffn {Config Command} {xlnx_axi_xvc dev_addr} addr
Specifies the address of the AXI-mapped registers via parameter @var{addr}.
The correct value for @var{addr} is specified in the "Address Editor" tab
in Vivado.
@end deffn
@end deffn
@deffn {Interface Driver} {bcm2835gpio}
This GPIO interface is present in Raspberry Pi 0-4 which is a cheap
single-board computer exposing some GPIOs on its expansion header.