jtag newtap change & huge manual update

git-svn-id: svn://svn.berlios.de/openocd/trunk@1194 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/board/arm_evaluator7t.cfg

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+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+# 
+# FIXME:
+#  Add (A) sdram configuration
+#  Add (B) flash cfi programing configuration
+#
+

src/target/board/at91rm9200-dk.cfg

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+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash_bank cfi 0x10000000 0x00200000 2 2 0
+
+
+proc at91rm9200_dk_init { } {
+    # Try to run at 1khz... Yea, that slow!
+    # Chip is really running @ 32khz
+    jtag_khz 8
+    
+    mww 0xfffffc64 0xffffffff
+    ##  disable all clocks but system clock
+    mww 0xfffffc04 0xfffffffe
+    ##  disable all clocks to pioa and piob
+    mww 0xfffffc14 0xffffffc3
+    ##  master clock = slow cpu = slow
+    ##  (means the CPU is running at 32khz!)
+    mww 0xfffffc30 0
+    ##  main osc enable
+    mww 0xfffffc20 0x0000ff01
+    ##  program pllA
+    mww 0xfffffc28 0x20263e04
+    ##  program pllB
+    mww 0xfffffc2c 0x10483e0e
+    ##  let pll settle... sleep 100msec
+    sleep 100
+    ##  switch to fast clock
+    mww 0xfffffc30 0x202
+    ## Sleep some - (go read)
+    sleep 100
+    
+    #========================================
+    # CPU now runs at 180mhz
+    # SYS runs at 60mhz.
+    jtag_khz 40000
+    #========================================
+    
+    
+    ##  set memc for all memories
+    mww 0xffffff60 0x02
+    ##  program smc controller
+    mww 0xffffff70 0x3284
+    ##  init sdram
+    mww 0xffffff98 0x7fffffd0
+    ##  all banks precharge
+    mww 0xffffff80 0x02
+    ##  touch sdram chip to make it work
+    mww 0x20000000 0
+    ##  sdram controller mode register 
+    mww 0xffffff90 0x04
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    ##  Refresh, etc....
+    mww 0xffffff90 0x03
+    mww 0x20000080 0
+    mww 0xffffff94 0x1f4
+    mww 0x20000080 0
+    mww 0xffffff90 0x10
+    mww 0x20000000 0
+    mww 0xffffff00 0x01
+
+}

src/target/board/eir.cfg

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+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# WDT_MR, disable watchdog 
+	mww 0xFFFFFD44 0x00008000
+
+	# RSTC_MR, enable user reset
+	mww 0xfffffd08 0xa5000001
+
+	# CKGR_MOR
+	mww 0xFFFFFC20 0x00000601
+	sleep 10
+
+	# CKGR_PLLR
+	mww 0xFFFFFC2C 0x00481c0e
+	sleep 10
+
+	# PMC_MCKR
+	mww 0xFFFFFC30 0x00000007
+	sleep 10
+
+	# PMC_IER
+	mww 0xFFFFFF60 0x00480100
+
+	#
+	# Enable SDRAM interface.
+	#
+
+	# Enable SDRAM control at PIO A.
+	mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+
+	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+	mww 0xfffff674 0x0003effd # PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+
+	# Enable 16 bit data bus at PIO C
+	mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+
+	# Enable SDRAM chip select
+	mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+
+	# Set SDRAM characteristics in configuration register.
+	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+	mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+	sleep 10
+
+	# Issue 16 bit SDRAM command: NOP
+	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 16 bit SDRAM command: Precharge all
+	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 8 auto-refresh cycles
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000 
+
+	# Issue 16 bit SDRAM command: Set mode register  
+	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+	mww 0x20000014 0xcafedede
+
+	# Set refresh rate count ???
+	mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+
+	# Issue 16 bit SDRAM command: Normal mode
+	mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+	mww 0x20000000 0x00000180
+
+	#
+	# Enable external reset key.
+	#
+	mww 0xfffffd08 0xa5000001
+}
+

src/target/board/hammer.cfg

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+# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
+# http://www.tincantools.com
+
+source [target/samsung_s3c2410.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# Reset Script for the TinCanTools S3C2410 Based Hammer Module
+	# http://www.tincantools.com
+	#
+	# Setup primary clocks and initialize the SDRAM
+	mww 0x53000000 0x00000000
+	mww 0x4a000008 0xffffffff
+	mww 0x4a00000c 0x000007ff
+	mww 0x4c000000 0x00ffffff
+	mww 0x4c000014 0x00000003
+	mww 0x4c000004 0x000a1031
+	mww 0x48000000 0x11111122
+	mww 0x48000004 0x00000700
+	mww 0x48000008 0x00000700
+	mww 0x4800000c 0x00000700
+	mww 0x48000010 0x00000700
+	mww 0x48000014 0x00000700
+	mww 0x48000018 0x00000700
+	mww 0x4800001c 0x00018005
+	mww 0x48000020 0x00018005
+	mww 0x48000024 0x009c0459
+	mww 0x48000028 0x000000b2
+	mww 0x4800002c 0x00000030
+	mww 0x48000030 0x00000030
+	flash probe 0
+}
+
+
+#flash configuration
+#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
+flash bank cfi 0x00000000 0x1000000 2 2 0

src/target/board/iar_str912_sk.cfg

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+# The IAR str912-sk evaluation kick start board has an str912
+
+source [find target/str912.cfg]

src/target/board/logicpd_imx27.cfg

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+# The LogicPD Eval IMX27 eval board has a single IMX27 chip
+source [find target/imx27.cfg]
+
+# The Logic PD board has a NOR flash on CS0
+flash_bank cfi 0xc0000000 0x00200000 2 2 0
+
+#
+# FIX ME, Add support to
+#
+# (A) hard reset the board.
+# (B) Initialize the SDRAM on the board
+#

src/target/board/olimex_sam7_ex256.cfg

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+# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
+
+source [find target/sam7x256.cfg]
+

src/target/board/stm3210e_eval.cfg

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+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+source [find target/stm32.cfg]

src/target/board/stm32f10x_128k_eval.cfg

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+# This is an STM32 eval board with a single STM32F103ZET6 chip on it.
+
+# My test board has a "Rev1" tap id.
+set BSTAPID 0x16410041
+source [find target/stm32.cfg]
+