aarch64: introduce dpm extension for ARMv8
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
@@ -38,6 +38,105 @@
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#include "target.h"
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#include "target_type.h"
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static const char * const armv8_state_strings[] = {
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"ARM", "Thumb", "Jazelle", "ThumbEE", "ARM64",
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};
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static const struct {
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const char *name;
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unsigned psr;
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/* For user and system modes, these list indices for all registers.
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* otherwise they're just indices for the shadow registers and SPSR.
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*/
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unsigned short n_indices;
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const uint8_t *indices;
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} armv8_mode_data[] = {
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/* These special modes are currently only supported
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* by ARMv6M and ARMv7M profiles */
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{
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.name = "EL0T",
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.psr = ARMV8_64_EL0T,
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},
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{
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.name = "EL1T",
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.psr = ARMV8_64_EL1T,
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},
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{
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.name = "EL1H",
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.psr = ARMV8_64_EL1H,
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},
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{
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.name = "EL2T",
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.psr = ARMV8_64_EL2T,
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},
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{
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.name = "EL2H",
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.psr = ARMV8_64_EL2H,
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},
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{
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.name = "EL3T",
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.psr = ARMV8_64_EL3T,
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},
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{
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.name = "EL3H",
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.psr = ARMV8_64_EL3H,
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},
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};
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/** Map PSR mode bits to the name of an ARM processor operating mode. */
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const char *armv8_mode_name(unsigned psr_mode)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
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if (armv8_mode_data[i].psr == psr_mode)
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return armv8_mode_data[i].name;
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}
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LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
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return "UNRECOGNIZED";
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}
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int armv8_mode_to_number(enum arm_mode mode)
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{
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switch (mode) {
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case ARM_MODE_ANY:
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/* map MODE_ANY to user mode */
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case ARM_MODE_USR:
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return 0;
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case ARM_MODE_FIQ:
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return 1;
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case ARM_MODE_IRQ:
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return 2;
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case ARM_MODE_SVC:
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return 3;
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case ARM_MODE_ABT:
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return 4;
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case ARM_MODE_UND:
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return 5;
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case ARM_MODE_SYS:
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return 6;
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case ARM_MODE_MON:
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return 7;
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case ARMV8_64_EL0T:
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return 8;
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case ARMV8_64_EL1T:
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return 9;
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case ARMV8_64_EL1H:
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return 10;
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case ARMV8_64_EL2T:
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return 11;
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case ARMV8_64_EL2H:
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return 12;
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case ARMV8_64_EL3T:
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return 13;
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case ARMV8_64_EL3H:
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return 14;
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default:
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LOG_ERROR("invalid mode value encountered %d", mode);
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return -1;
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}
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}
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static int armv8_read_core_reg(struct target *target, struct reg *r,
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int num, enum arm_mode mode)
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{
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@@ -86,6 +185,81 @@ static int armv8_write_core_reg(struct target *target, struct reg *r,
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return ERROR_OK;
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}
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#endif
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/**
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* Configures host-side ARM records to reflect the specified CPSR.
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* Later, code can use arm_reg_current() to map register numbers
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* according to how they are exposed by this mode.
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*/
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void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
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{
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uint32_t mode = cpsr & 0x1F;
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/* NOTE: this may be called very early, before the register
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* cache is set up. We can't defend against many errors, in
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* particular against CPSRs that aren't valid *here* ...
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*/
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if (arm->cpsr) {
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buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
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arm->cpsr->valid = 1;
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arm->cpsr->dirty = 0;
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}
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/* Older ARMs won't have the J bit */
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enum arm_state state = 0xFF;
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if (((cpsr & 0x10) >> 4) == 0) {
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state = ARM_STATE_AARCH64;
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} else {
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if (cpsr & (1 << 5)) { /* T */
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if (cpsr & (1 << 24)) { /* J */
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LOG_WARNING("ThumbEE -- incomplete support");
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state = ARM_STATE_THUMB_EE;
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} else
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state = ARM_STATE_THUMB;
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} else {
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if (cpsr & (1 << 24)) { /* J */
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LOG_ERROR("Jazelle state handling is BROKEN!");
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state = ARM_STATE_JAZELLE;
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} else
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state = ARM_STATE_ARM;
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}
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}
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arm->core_state = state;
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if (arm->core_state == ARM_STATE_AARCH64) {
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switch (mode) {
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case SYSTEM_AAR64_MODE_EL0t:
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arm->core_mode = ARMV8_64_EL0T;
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break;
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case SYSTEM_AAR64_MODE_EL1t:
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arm->core_mode = ARMV8_64_EL0T;
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break;
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case SYSTEM_AAR64_MODE_EL1h:
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arm->core_mode = ARMV8_64_EL1H;
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break;
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case SYSTEM_AAR64_MODE_EL2t:
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arm->core_mode = ARMV8_64_EL2T;
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break;
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case SYSTEM_AAR64_MODE_EL2h:
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arm->core_mode = ARMV8_64_EL2H;
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break;
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case SYSTEM_AAR64_MODE_EL3t:
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arm->core_mode = ARMV8_64_EL3T;
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break;
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case SYSTEM_AAR64_MODE_EL3h:
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arm->core_mode = ARMV8_64_EL3H;
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break;
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default:
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LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
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break;
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}
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} else {
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arm->core_mode = mode;
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}
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LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
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armv8_mode_name(arm->core_mode),
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armv8_state_strings[arm->core_state]);
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}
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static void armv8_show_fault_registers(struct target *target)
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{
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