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target/cortex_m: Implement maskisr steponly option

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`maskisr steponly` disables interrupts during single-stepping but
enables them during normal execution. This can be used as a partial
workaround for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610)
and Cortex-M7 with FPU (AT611) Software Developer Errata Notice" from
ARM for further details.

Change-Id: I797a14e4d43f6dcb3706528ee4ab452846ebf133
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4673
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Christopher Head
2018-08-01 10:21:15 -07:00
committed by Freddie Chopin
parent 5b263d7b0c
commit a4ac56152d
3 changed files with 127 additions and 26 deletions
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7
doc/openocd.texi
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@@ -9078,7 +9078,7 @@ Enable or disable trace output for all ITM stimulus ports.
@subsection Cortex-M specific commands
@cindex Cortex-M
@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
Control masking (disabling) interrupts during target step/resume.
The @option{auto} option handles interrupts during stepping in a way that they
@@ -9088,6 +9088,11 @@ the next instruction where the core was halted. After the step interrupts
are enabled again. If the interrupt handlers don't complete within 500ms,
the step command leaves with the core running.
The @option{steponly} option disables interrupts during single-stepping but
enables them during normal execution. This can be used as a partial workaround
for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
FPU (AT611) Software Developer Errata Notice" from ARM for further details.
Note that a free hardware (FPB) breakpoint is required for the @option{auto}
option. If no breakpoint is available at the time of the step, then the step
is taken with interrupts enabled, i.e. the same way the @option{off} option