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target/cortex_m: Implement maskisr steponly option

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`maskisr steponly` disables interrupts during single-stepping but
enables them during normal execution. This can be used as a partial
workaround for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610)
and Cortex-M7 with FPU (AT611) Software Developer Errata Notice" from
ARM for further details.

Change-Id: I797a14e4d43f6dcb3706528ee4ab452846ebf133
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4673
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Christopher Head
2018-08-01 10:21:15 -07:00
committed by Freddie Chopin
parent 5b263d7b0c
commit a4ac56152d
3 changed files with 127 additions and 26 deletions
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5
src/target/cortex_m.h
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@@ -159,6 +159,7 @@ enum cortex_m_isrmasking_mode {
CORTEX_M_ISRMASK_AUTO,
CORTEX_M_ISRMASK_OFF,
CORTEX_M_ISRMASK_ON,
CORTEX_M_ISRMASK_STEPONLY,
};
struct cortex_m_common {
@@ -190,6 +191,10 @@ struct cortex_m_common {
struct armv7m_common armv7m;
int apsel;
/* Whether this target has the erratum that makes C_MASKINTS not apply to
* already pending interrupts */
bool maskints_erratum;
};
static inline struct cortex_m_common *