Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec. Support for `-rtos riscv` will come in a separate commit since it was easy to separate out, and is likely to be more controversial. Flash support for the SiFive boards will also come in a later commit. Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4578 Tested-by: jenkins Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Tim Newsome
committed by
Matthias Welwarsky
Matthias Welwarsky
parent
9363705820
commit
a51ab8ddf6
262
src/target/riscv/riscv.h
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262
src/target/riscv/riscv.h
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#ifndef RISCV_H
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#define RISCV_H
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struct riscv_program;
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#include <stdint.h>
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#include "opcodes.h"
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#include "gdb_regs.h"
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/* The register cache is statically allocated. */
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#define RISCV_MAX_HARTS 32
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#define RISCV_MAX_REGISTERS 5000
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#define RISCV_MAX_TRIGGERS 32
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#define RISCV_MAX_HWBPS 16
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#define DEFAULT_COMMAND_TIMEOUT_SEC 2
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#define DEFAULT_RESET_TIMEOUT_SEC 30
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extern struct target_type riscv011_target;
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extern struct target_type riscv013_target;
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/*
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* Definitions shared by code supporting all RISC-V versions.
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*/
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typedef uint64_t riscv_reg_t;
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typedef uint32_t riscv_insn_t;
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typedef uint64_t riscv_addr_t;
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enum riscv_halt_reason {
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RISCV_HALT_INTERRUPT,
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RISCV_HALT_BREAKPOINT,
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RISCV_HALT_SINGLESTEP,
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RISCV_HALT_TRIGGER,
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RISCV_HALT_UNKNOWN,
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RISCV_HALT_ERROR
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};
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typedef struct {
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unsigned dtm_version;
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struct command_context *cmd_ctx;
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void *version_specific;
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/* The number of harts on this system. */
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int hart_count;
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/* The hart that the RTOS thinks is currently being debugged. */
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int rtos_hartid;
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/* The hart that is currently being debugged. Note that this is
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* different than the hartid that the RTOS is expected to use. This
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* one will change all the time, it's more of a global argument to
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* every function than an actual */
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int current_hartid;
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/* Enough space to store all the registers we might need to save. */
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/* FIXME: This should probably be a bunch of register caches. */
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uint64_t saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
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bool valid_saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
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/* OpenOCD's register cache points into here. This is not per-hart because
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* we just invalidate the entire cache when we change which hart is
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* selected. */
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uint64_t reg_cache_values[RISCV_MAX_REGISTERS];
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/* Single buffer that contains all register names, instead of calling
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* malloc for each register. Needs to be freed when reg_list is freed. */
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char *reg_names;
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/* It's possible that each core has a different supported ISA set. */
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int xlen[RISCV_MAX_HARTS];
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riscv_reg_t misa[RISCV_MAX_HARTS];
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/* The number of triggers per hart. */
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unsigned trigger_count[RISCV_MAX_HARTS];
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/* For each physical trigger, contains -1 if the hwbp is available, or the
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* unique_id of the breakpoint/watchpoint that is using it.
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* Note that in RTOS mode the triggers are the same across all harts the
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* target controls, while otherwise only a single hart is controlled. */
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int trigger_unique_id[RISCV_MAX_HWBPS];
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/* The number of entries in the debug buffer. */
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int debug_buffer_size[RISCV_MAX_HARTS];
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/* This avoids invalidating the register cache too often. */
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bool registers_initialized;
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/* This hart contains an implicit ebreak at the end of the program buffer. */
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bool impebreak;
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bool triggers_enumerated;
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/* Helper functions that target the various RISC-V debug spec
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* implementations. */
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int (*get_register)(struct target *target,
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riscv_reg_t *value, int hid, int rid);
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int (*set_register)(struct target *, int hartid, int regid,
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uint64_t value);
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int (*select_current_hart)(struct target *);
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bool (*is_halted)(struct target *target);
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int (*halt_current_hart)(struct target *);
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int (*resume_current_hart)(struct target *target);
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int (*step_current_hart)(struct target *target);
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int (*on_halt)(struct target *target);
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int (*on_resume)(struct target *target);
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int (*on_step)(struct target *target);
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enum riscv_halt_reason (*halt_reason)(struct target *target);
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int (*write_debug_buffer)(struct target *target, unsigned index,
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riscv_insn_t d);
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riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
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int (*execute_debug_buffer)(struct target *target);
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int (*dmi_write_u64_bits)(struct target *target);
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void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
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void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
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void (*fill_dmi_nop_u64)(struct target *target, char *buf);
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int (*authdata_read)(struct target *target, uint32_t *value);
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int (*authdata_write)(struct target *target, uint32_t value);
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int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
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int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
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} riscv_info_t;
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/* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
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extern int riscv_command_timeout_sec;
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/* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
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extern int riscv_reset_timeout_sec;
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extern bool riscv_prefer_sba;
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/* Everything needs the RISC-V specific info structure, so here's a nice macro
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* that provides that. */
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static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
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static inline riscv_info_t *riscv_info(const struct target *target)
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{ return target->arch_info; }
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#define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
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extern uint8_t ir_dtmcontrol[1];
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extern struct scan_field select_dtmcontrol;
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extern uint8_t ir_dbus[1];
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extern struct scan_field select_dbus;
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extern uint8_t ir_idcode[1];
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extern struct scan_field select_idcode;
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/*** OpenOCD Interface */
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int riscv_openocd_poll(struct target *target);
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int riscv_openocd_halt(struct target *target);
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int riscv_openocd_resume(
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struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints,
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int debug_execution
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);
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int riscv_openocd_step(
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struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints
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);
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int riscv_openocd_assert_reset(struct target *target);
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int riscv_openocd_deassert_reset(struct target *target);
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/*** RISC-V Interface ***/
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/* Initializes the shared RISC-V structure. */
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void riscv_info_init(struct target *target, riscv_info_t *r);
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/* Run control, possibly for multiple harts. The _all_harts versions resume
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* all the enabled harts, which when running in RTOS mode is all the harts on
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* the system. */
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int riscv_halt_all_harts(struct target *target);
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int riscv_halt_one_hart(struct target *target, int hartid);
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int riscv_resume_all_harts(struct target *target);
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int riscv_resume_one_hart(struct target *target, int hartid);
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/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
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* then the only hart. */
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int riscv_step_rtos_hart(struct target *target);
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bool riscv_supports_extension(struct target *target, int hartid, char letter);
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/* Returns XLEN for the given (or current) hart. */
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int riscv_xlen(const struct target *target);
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int riscv_xlen_of_hart(const struct target *target, int hartid);
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bool riscv_rtos_enabled(const struct target *target);
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/* Sets the current hart, which is the hart that will actually be used when
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* issuing debug commands. */
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int riscv_set_current_hartid(struct target *target, int hartid);
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int riscv_current_hartid(const struct target *target);
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/*** Support functions for the RISC-V 'RTOS', which provides multihart support
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* without requiring multiple targets. */
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/* When using the RTOS to debug, this selects the hart that is currently being
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* debugged. This doesn't propogate to the hardware. */
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void riscv_set_all_rtos_harts(struct target *target);
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void riscv_set_rtos_hartid(struct target *target, int hartid);
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/* Lists the number of harts in the system, which are assumed to be
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* concecutive and start with mhartid=0. */
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int riscv_count_harts(struct target *target);
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/* Returns TRUE if the target has the given register on the given hart. */
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bool riscv_has_register(struct target *target, int hartid, int regid);
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/* Returns the value of the given register on the given hart. 32-bit registers
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* are zero extended to 64 bits. */
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int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
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int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
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int riscv_get_register(struct target *target, riscv_reg_t *value,
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enum gdb_regno r);
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int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
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int hartid, enum gdb_regno regid);
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/* Checks the state of the current hart -- "is_halted" checks the actual
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* on-device register. */
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bool riscv_is_halted(struct target *target);
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enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
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/* These helper functions let the generic program interface get target-specific
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* information. */
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size_t riscv_debug_buffer_size(struct target *target);
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riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
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int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
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int riscv_execute_debug_buffer(struct target *target);
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void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
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void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
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void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
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int riscv_dmi_write_u64_bits(struct target *target);
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/* Invalidates the register cache. */
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void riscv_invalidate_register_cache(struct target *target);
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/* Returns TRUE when a hart is enabled in this target. */
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bool riscv_hart_enabled(struct target *target, int hartid);
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int riscv_enumerate_triggers(struct target *target);
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int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
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int riscv_remove_breakpoint(struct target *target,
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struct breakpoint *breakpoint);
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int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
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int riscv_remove_watchpoint(struct target *target,
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struct watchpoint *watchpoint);
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int riscv_init_registers(struct target *target);
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void riscv_semihosting_init(struct target *target);
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int riscv_semihosting(struct target *target, int *retval);
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#endif
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