Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec. Support for `-rtos riscv` will come in a separate commit since it was easy to separate out, and is likely to be more controversial. Flash support for the SiFive boards will also come in a later commit. Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4578 Tested-by: jenkins Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
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Tim Newsome
committed by
Matthias Welwarsky
Matthias Welwarsky
parent
9363705820
commit
a51ab8ddf6
194
src/target/riscv/riscv_semihosting.c
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194
src/target/riscv/riscv_semihosting.c
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/***************************************************************************
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* Copyright (C) 2018 by Liviu Ionescu *
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* ilg@livius.net *
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* *
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* Copyright (C) 2009 by Marvell Technology Group Ltd. *
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* Written by Nicolas Pitre <nico@marvell.com> *
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* *
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2016 by Square, Inc. *
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* Steven Stallion <stallion@squareup.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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/**
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* @file
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* Hold RISC-V semihosting support.
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*
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* The RISC-V code is inspired from ARM semihosting.
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*
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* Details can be found in chapter 8 of DUI0203I_rvct_developer_guide.pdf
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* from ARM Ltd.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "log.h"
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#include "target/target.h"
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#include "target/semihosting_common.h"
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#include "riscv.h"
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static int riscv_semihosting_setup(struct target *target, int enable);
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static int riscv_semihosting_post_result(struct target *target);
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/**
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* Initialize RISC-V semihosting. Use common ARM code.
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*/
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void riscv_semihosting_init(struct target *target)
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{
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semihosting_common_init(target, riscv_semihosting_setup,
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riscv_semihosting_post_result);
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}
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/**
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* Check for and process a semihosting request using the ARM protocol). This
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* is meant to be called when the target is stopped due to a debug mode entry.
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* If the value 0 is returned then there was nothing to process. A non-zero
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* return value signifies that a request was processed and the target resumed,
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* or an error was encountered, in which case the caller must return
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* immediately.
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*
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* @param target Pointer to the target to process.
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* @param retval Pointer to a location where the return code will be stored
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* @return non-zero value if a request was processed or an error encountered
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*/
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int riscv_semihosting(struct target *target, int *retval)
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{
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struct semihosting *semihosting = target->semihosting;
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if (!semihosting)
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return 0;
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if (!semihosting->is_active)
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return 0;
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riscv_reg_t dpc;
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int result = riscv_get_register(target, &dpc, GDB_REGNO_DPC);
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if (result != ERROR_OK)
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return 0;
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uint8_t tmp[12];
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/* Read the current instruction, including the bracketing */
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*retval = target_read_memory(target, dpc - 4, 2, 6, tmp);
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if (*retval != ERROR_OK)
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return 0;
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/*
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* The instructions that trigger a semihosting call,
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* always uncompressed, should look like:
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*
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* 01f01013 slli zero,zero,0x1f
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* 00100073 ebreak
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* 40705013 srai zero,zero,0x7
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*/
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uint32_t pre = target_buffer_get_u32(target, tmp);
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uint32_t ebreak = target_buffer_get_u32(target, tmp + 4);
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uint32_t post = target_buffer_get_u32(target, tmp + 8);
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LOG_DEBUG("check %08x %08x %08x from 0x%" PRIx64 "-4", pre, ebreak, post, dpc);
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if (pre != 0x01f01013 || ebreak != 0x00100073 || post != 0x40705013) {
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/* Not the magic sequence defining semihosting. */
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return 0;
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}
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/*
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* Perform semihosting call if we are not waiting on a fileio
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* operation to complete.
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*/
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if (!semihosting->hit_fileio) {
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/* RISC-V uses A0 and A1 to pass function arguments */
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riscv_reg_t r0;
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riscv_reg_t r1;
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result = riscv_get_register(target, &r0, GDB_REGNO_A0);
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if (result != ERROR_OK)
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return 0;
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result = riscv_get_register(target, &r1, GDB_REGNO_A1);
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if (result != ERROR_OK)
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return 0;
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semihosting->op = r0;
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semihosting->param = r1;
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semihosting->word_size_bytes = riscv_xlen(target) / 8;
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/* Check for ARM operation numbers. */
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if (0 <= semihosting->op && semihosting->op <= 0x31) {
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*retval = semihosting_common(target);
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if (*retval != ERROR_OK) {
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LOG_ERROR("Failed semihosting operation");
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return 0;
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}
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} else {
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/* Unknown operation number, not a semihosting call. */
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return 0;
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}
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}
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/*
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* Resume target if we are not waiting on a fileio
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* operation to complete.
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*/
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if (semihosting->is_resumable && !semihosting->hit_fileio) {
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/* Resume right after the EBREAK 4 bytes instruction. */
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*retval = target_resume(target, 0, dpc+4, 0, 0);
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if (*retval != ERROR_OK) {
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LOG_ERROR("Failed to resume target");
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return 0;
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}
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return 1;
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}
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return 0;
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}
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/* -------------------------------------------------------------------------
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* Local functions. */
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/**
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* Called via semihosting->setup() later, after the target is known,
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* usually on the first semihosting command.
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*/
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static int riscv_semihosting_setup(struct target *target, int enable)
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{
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LOG_DEBUG("enable=%d", enable);
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struct semihosting *semihosting = target->semihosting;
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if (semihosting)
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semihosting->setup_time = clock();
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return ERROR_OK;
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}
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static int riscv_semihosting_post_result(struct target *target)
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{
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struct semihosting *semihosting = target->semihosting;
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if (!semihosting) {
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/* If not enabled, silently ignored. */
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return 0;
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}
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LOG_DEBUG("0x%" PRIx64, semihosting->result);
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riscv_set_register(target, GDB_REGNO_A0, semihosting->result);
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return 0;
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}
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