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target/adiv5: Large Physical Address Extension

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Provides ARM LPAE support to allow 64-bit TAR setting
on MEM AP accesses.

Tested on a 4-core ARM ARES Processor system using an
AXI Access Port.

Change-Id: I88f7a0a57a6abb58665032929194a41dd8729f6b
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/5576
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Kevin Burke
2021-02-09 17:27:03 -05:00
committed by Antonio Borneo
parent 920cacd74c
commit ac22cdc573
7 changed files with 168 additions and 74 deletions
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6
src/target/aarch64.c
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@@ -252,7 +252,7 @@ static int aarch64_init_debug_access(struct target *target)
/* Write to memory mapped registers directly with no cache or mmu handling */
static int aarch64_dap_write_memap_register_u32(struct target *target,
uint32_t address,
target_addr_t address,
uint32_t value)
{
int retval;
@@ -2571,7 +2571,7 @@ static int aarch64_examine_first(struct target *target)
armv8->debug_ap->memaccess_tck = 10;
if (!target->dbgbase_set) {
uint32_t dbgbase;
target_addr_t dbgbase;
/* Get ROM Table base */
uint32_t apid;
int32_t coreidx = target->coreid;
@@ -2583,7 +2583,7 @@ static int aarch64_examine_first(struct target *target)
&armv8->debug_base, &coreidx);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32
LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT
" apid: %08" PRIx32, coreidx, armv8->debug_base, apid);
} else
armv8->debug_base = target->dbgbase;