diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index cfb40433b..6823fc60f 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -755,7 +755,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 								| F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0FF907A0,
-	  .otp_base              = 0x0FF90000,
+	  .otp_base              = 0x0BF90000,
 	  .otp_size              = 512,
 	},
 	{
diff --git a/tcl/target/stm32wba5x.cfg b/tcl/target/stm32wba5x.cfg
index ea6544bf5..704174db4 100644
--- a/tcl/target/stm32wba5x.cfg
+++ b/tcl/target/stm32wba5x.cfg
@@ -47,7 +47,7 @@ target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x0bf90000 0 0 0 $_TARGETNAME
 
 # Common knowledges tells JTAG speed should be <= F_CPU/6.
 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
@@ -88,12 +88,12 @@ $_TARGETNAME configure -event reset-start {
 
 $_TARGETNAME configure -event examine-end {
     # Enable debug during low power modes (uses more power)
-    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-    mmw 0xE0042004 0x00000006 0
+    # DBGMCU_SCR |= DBG_STANDBY | DBG_STOP
+    mmw 0xE0044004 0x00000006 0
 
     # Stop watchdog counters during halt
     # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
-    mmw 0xE0042008 0x00001800 0
+    mmw 0xE0044008 0x00001800 0
 }
 
 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000